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| author | Bharat Bhushan <Bharat.Bhushan@freescale.com> | 2013-01-16 02:24:43 +0400 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2013-02-13 15:56:42 +0400 |
| commit | ee53e560a8f52cbc1fba877fdf4acffb0c163f29 (patch) | |
| tree | dbd900c75fedce8497bacd3d83209a75523d6616 /arch/powerpc/include | |
| parent | 1d542d9c2bbca9b99835fef6a938b9ae9dd7ca2a (diff) | |
| download | linux-ee53e560a8f52cbc1fba877fdf4acffb0c163f29.tar.xz | |
booke: Added DBCR4 SPR number
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/reg_booke.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index e07e6af5e1ff..b417de3cc2c4 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -56,6 +56,7 @@ #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ #define SPRN_EPCR 0x133 /* Embedded Processor Control Register */ #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ +#define SPRN_DBCR4 0x233 /* Debug Control Register 4 */ #define SPRN_MSRP 0x137 /* MSR Protect Register */ #define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ #define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ |