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author | Linus Torvalds <torvalds@linux-foundation.org> | 2023-08-11 19:12:44 +0300 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-08-11 19:12:44 +0300 |
commit | 2a3c17edbf53816ba61746c38833b48c73ee2a16 (patch) | |
tree | 4beb6331813a1ae02dd397ac5802c73956d4ad57 /arch/powerpc/include/asm/hw_breakpoint.h | |
parent | feb0eee9aa3c85aa15e3b60f82cb8d1fae28f2fe (diff) | |
parent | 7e3811521dc3934e2ecae8458676fc4a1f62bf9f (diff) | |
download | linux-2a3c17edbf53816ba61746c38833b48c73ee2a16.tar.xz |
Merge tag 'riscv-for-linus-6.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fixes from Palmer Dabbelt:
- Fixes for a pair of kexec_file_load() failures
- A fix to ensure the direct mapping is PMD-aligned
- A fix for CPU feature detection on SMP=n
- The MMIO ordering fences have been strengthened to ensure ordering
WRT delay()
- Fixes for a pair of -Wmissing-variable-declarations warnings
- A fix to avoid PUD mappings in vmap on sv39
- flush_cache_vmap() now flushes the TLB to avoid issues on systems
that cache invalid mappings
* tag 'riscv-for-linus-6.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: Implement flush_cache_vmap()
riscv: Do not allow vmap pud mappings for 3-level page table
riscv: mm: fix 2 instances of -Wmissing-variable-declarations
riscv,mmio: Fix readX()-to-delay() ordering
riscv: Fix CPU feature detection with SMP disabled
riscv: Start of DRAM should at least be aligned on PMD size for the direct mapping
riscv/kexec: load initrd high in available memory
riscv/kexec: handle R_RISCV_CALL_PLT relocation type
Diffstat (limited to 'arch/powerpc/include/asm/hw_breakpoint.h')
0 files changed, 0 insertions, 0 deletions