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authorSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>2020-09-03 12:38:22 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2020-09-26 19:03:15 +0300
commit071f42defada1da666a95a53866f6efe4e335cc7 (patch)
tree250242c6ccd73ede4927e4ec19f2e47254a7b47e /arch/powerpc/include/asm/dcr-mmio.h
parenta5bc1c7a9a6d64f2f76b43ffe2c644b40e063cfd (diff)
downloadlinux-071f42defada1da666a95a53866f6efe4e335cc7.tar.xz
iommu/amd: Use cmpxchg_double() when updating 128-bit IRTE
commit e52d58d54a321d4fe9d0ecdabe4f8774449f0d6e upstream. When using 128-bit interrupt-remapping table entry (IRTE) (a.k.a GA mode), current driver disables interrupt remapping when it updates the IRTE so that the upper and lower 64-bit values can be updated safely. However, this creates a small window, where the interrupt could arrive and result in IO_PAGE_FAULT (for interrupt) as shown below. IOMMU Driver Device IRQ ============ =========== irte.RemapEn=0 ... change IRTE IRQ from device ==> IO_PAGE_FAULT !! ... irte.RemapEn=1 This scenario has been observed when changing irq affinity on a system running I/O-intensive workload, in which the destination APIC ID in the IRTE is updated. Instead, use cmpxchg_double() to update the 128-bit IRTE at once without disabling the interrupt remapping. However, this means several features, which require GA (128-bit IRTE) support will also be affected if cmpxchg16b is not supported (which is unprecedented for AMD processors w/ IOMMU). Fixes: 880ac60e2538 ("iommu/amd: Introduce interrupt remapping ops structure") Reported-by: Sean Osborne <sean.m.osborne@oracle.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Tested-by: Erik Rockstrom <erik.rockstrom@oracle.com> Reviewed-by: Joao Martins <joao.m.martins@oracle.com> Link: https://lore.kernel.org/r/20200903093822.52012-3-suravee.suthikulpanit@amd.com Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/powerpc/include/asm/dcr-mmio.h')
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