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authorPrabhakar Kushwaha <prabhakar@freescale.com>2011-04-20 08:12:44 +0400
committerKumar Gala <galak@kernel.crashing.org>2011-05-19 10:15:42 +0400
commitbc99d09abe14b4841454701c47e45f22444a890a (patch)
tree5ac103e873a71c79aaac561678f96816e187e77a /arch/powerpc/boot/dts/p2020rdb.dts
parenteb2c5d9965adec2d7cd1946fa39f2dece073dab7 (diff)
downloadlinux-bc99d09abe14b4841454701c47e45f22444a890a.tar.xz
powerpc/85xx: Fix PCIe IDSEL for Px020RDB
PCIe device in legacy mode can trigger interrupts using the wires #INTA, #INTB ,#INTC and #INTD. PCI devices are obligated to use #INTx for interrupts under legacy mode. Each PCI slot or device is typically wired to different inputs on the interrupt controller. So, Define interrupt-map and interrupt-map-mask properties for device tree to of map each PCI interrupt signal to the inputs of the interrupt controller. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/p2020rdb.dts')
-rw-r--r--arch/powerpc/boot/dts/p2020rdb.dts16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
index 60a0a8c725d6..3782a58f13be 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -249,6 +249,14 @@
pci1: pcie@ffe09000 {
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0x0 0x0 0x1 &mpic 0x4 0x1
+ 0000 0x0 0x0 0x2 &mpic 0x5 0x1
+ 0000 0x0 0x0 0x3 &mpic 0x6 0x1
+ 0000 0x0 0x0 0x4 &mpic 0x7 0x1
+ >;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
@@ -267,6 +275,14 @@
pci2: pcie@ffe0a000 {
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0000 0x0 0x0 0x4 &mpic 0x3 0x1
+ >;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;