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| author | Stephen George <Stephen.George@freescale.com> | 2013-03-05 23:44:34 +0400 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2013-03-18 23:09:00 +0400 |
| commit | 8c33de98fec2c6350a4e6b8d6f56afd312acf4cc (patch) | |
| tree | 17354f4b5992de72bec35d4e946bb13aaf541cac /arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi | |
| parent | 5274bf9b986af91ea0378a504260aeb0e2a7d25f (diff) | |
| download | linux-8c33de98fec2c6350a4e6b8d6f56afd312acf4cc.tar.xz | |
powerpc/fsl-booke: Added device tree DCSR entries for T4240 Chassis v2 Debug IP
Signed-off-by: Stephen George <Stephen.George@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi')
| -rw-r--r-- | arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi index 12af298a9aa0..9b39a438d691 100644 --- a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi +++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi @@ -44,6 +44,7 @@ aliases { ccsr = &soc; + dcsr = &dcsr; serial0 = &serial0; serial1 = &serial1; @@ -63,62 +64,62 @@ #address-cells = <1>; #size-cells = <0>; - PowerPC,e6500@0 { + cpu0: PowerPC,e6500@0 { device_type = "cpu"; reg = <0 1>; next-level-cache = <&L2_1>; }; - PowerPC,e6500@1 { + cpu1: PowerPC,e6500@1 { device_type = "cpu"; reg = <2 3>; next-level-cache = <&L2_1>; }; - PowerPC,e6500@2 { + cpu2: PowerPC,e6500@2 { device_type = "cpu"; reg = <4 5>; next-level-cache = <&L2_1>; }; - PowerPC,e6500@3 { + cpu3: PowerPC,e6500@3 { device_type = "cpu"; reg = <6 7>; next-level-cache = <&L2_1>; }; - PowerPC,e6500@4 { + cpu4: PowerPC,e6500@4 { device_type = "cpu"; reg = <8 9>; next-level-cache = <&L2_2>; }; - PowerPC,e6500@5 { + cpu5: PowerPC,e6500@5 { device_type = "cpu"; reg = <10 11>; next-level-cache = <&L2_2>; }; - PowerPC,e6500@6 { + cpu6: PowerPC,e6500@6 { device_type = "cpu"; reg = <12 13>; next-level-cache = <&L2_2>; }; - PowerPC,e6500@7 { + cpu7: PowerPC,e6500@7 { device_type = "cpu"; reg = <14 15>; next-level-cache = <&L2_2>; }; - PowerPC,e6500@8 { + cpu8: PowerPC,e6500@8 { device_type = "cpu"; reg = <16 17>; next-level-cache = <&L2_3>; }; - PowerPC,e6500@9 { + cpu9: PowerPC,e6500@9 { device_type = "cpu"; reg = <18 19>; next-level-cache = <&L2_3>; }; - PowerPC,e6500@10 { + cpu10: PowerPC,e6500@10 { device_type = "cpu"; reg = <20 21>; next-level-cache = <&L2_3>; }; - PowerPC,e6500@11 { + cpu11: PowerPC,e6500@11 { device_type = "cpu"; reg = <22 23>; next-level-cache = <&L2_3>; |