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author | Kevin Hilman <khilman@linaro.org> | 2014-12-16 00:59:43 +0300 |
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committer | Kevin Hilman <khilman@linaro.org> | 2014-12-16 00:59:43 +0300 |
commit | 1888d2fa314033755026ceddee1fff8f80659fe4 (patch) | |
tree | b0085323f5db6dca5f259b92038e27843c5a43a6 /arch/nios2/platform | |
parent | 9d312cd12e89ce08add99fe66e8f6baeaca16d7d (diff) | |
parent | 661ea91b676bcca137c1c3fe838997925ce98060 (diff) | |
download | linux-1888d2fa314033755026ceddee1fff8f80659fe4.tar.xz |
Merge tag 'omap-for-v3.19/fixes-for-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
From: Tony Lindgren <tony@atomide.com>
Subject: [GIT PULL] few fixes for the v3.19 merge window
Fixes for a few issues found that would be good to get
into -rc1:
- Update SoC revision detection for am43x es1.2
- Fix regression with GPMC timings on 2430sdp for some versions
of u-boot
- Fix dra7 watchdog compatible property
- Fix am437x-sk-evm LCD timings
- Fix dra7 DSS clock muxing
- Fix dra7-evm voltages
- Remove a unused function prototype for am33xx_clk_init
- Enable AHCI in the omap2plus_defconfig
* tag 'omap-for-v3.19/fixes-for-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (1601 commits)
ARM: omap2plus_defconfig: Enable AHCI_PLATFORM driver
ARM: dts: am437x-sk-evm.dts: fix LCD timings
ARM: dts: dra7-evm: Update SMPS7 (VDD_CORE) max voltage to match DM
ARM: dts: dra7-evm: Fix typo in SMPS6 (VDD_GPU) max voltage
ARM: OMAP2+: AM43x: Add ID for ES1.2
ARM: dts: am437x-sk: fix lcd enable pin mux data
ARM: dts: Fix gpmc regression for omap 2430sdp smc91x
hwmon: (tmp401) Detect TMP435 on all addresses it supports
mfd: rtsx: Add func to split u32 into register
mmc: sdhci-msm: Convert to mmc_send_tuning()
mmc: sdhci-esdhc-imx: Convert to mmc_send_tuning()
mmc: core: Let mmc_send_tuning() to take struct mmc_host* as parameter
nios2: Make NIOS2_CMDLINE_IGNORE_DTB depend on CMDLINE_BOOL
nios2: Add missing NR_CPUS to Kconfig
nios2: asm-offsets: Remove unused definition TI_TASK
nios2: Remove write-only struct member from nios2_timer
nios2: Remove unused extern declaration of shm_align_mask
nios2: include linux/type.h in io.h
nios2: move include asm-generic/io.h to end of file
nios2: remove include asm-generic/iomap.h from io.h
...
Diffstat (limited to 'arch/nios2/platform')
-rw-r--r-- | arch/nios2/platform/Kconfig.platform | 129 | ||||
-rw-r--r-- | arch/nios2/platform/Makefile | 1 | ||||
-rw-r--r-- | arch/nios2/platform/platform.c | 46 |
3 files changed, 176 insertions, 0 deletions
diff --git a/arch/nios2/platform/Kconfig.platform b/arch/nios2/platform/Kconfig.platform new file mode 100644 index 000000000000..d3e5df9fb36b --- /dev/null +++ b/arch/nios2/platform/Kconfig.platform @@ -0,0 +1,129 @@ +menu "Platform options" + +comment "Memory settings" + +config NIOS2_MEM_BASE + hex "Memory base address" + default "0x00000000" + help + This is the physical address of the memory that the kernel will run + from. This address is used to link the kernel and setup initial memory + management. You should take the raw memory address without any MMU + or cache bits set. + Please not that this address is used directly so you have to manually + do address translation if it's connected to a bridge. + +comment "Device tree" + +config NIOS2_DTB_AT_PHYS_ADDR + bool "DTB at physical address" + default n + help + When enabled you can select a physical address to load the dtb from. + Normally this address is passed by a bootloader such as u-boot but + using this you can use a devicetree without a bootloader. + This way you can store a devicetree in NOR flash or an onchip rom. + Please note that this address is used directly so you have to manually + do address translation if it's connected to a bridge. Also take into + account that when using an MMU you'd have to ad 0xC0000000 to your + address + +config NIOS2_DTB_PHYS_ADDR + hex "DTB Address" + depends on NIOS2_DTB_AT_PHYS_ADDR + default "0xC0000000" + help + Physical address of a dtb blob. + +config NIOS2_DTB_SOURCE_BOOL + bool "Compile and link device tree into kernel image" + default n + help + This allows you to specify a dts (device tree source) file + which will be compiled and linked into the kernel image. + +config NIOS2_DTB_SOURCE + string "Device tree source file" + depends on NIOS2_DTB_SOURCE_BOOL + default "" + help + Absolute path to the device tree source (dts) file describing your + system. + +comment "Nios II instructions" + +config NIOS2_HW_MUL_SUPPORT + bool "Enable MUL instruction" + default n + help + Set to true if you configured the Nios II to include the MUL + instruction. This will enable the -mhw-mul compiler flag. + +config NIOS2_HW_MULX_SUPPORT + bool "Enable MULX instruction" + default n + help + Set to true if you configured the Nios II to include the MULX + instruction. Enables the -mhw-mulx compiler flag. + +config NIOS2_HW_DIV_SUPPORT + bool "Enable DIV instruction" + default n + help + Set to true if you configured the Nios II to include the DIV + instruction. Enables the -mhw-div compiler flag. + +config NIOS2_FPU_SUPPORT + bool "Custom floating point instr support" + default n + help + Enables the -mcustom-fpu-cfg=60-1 compiler flag. + +config NIOS2_CI_SWAB_SUPPORT + bool "Byteswap custom instruction" + default n + help + Use the byteswap (endian converter) Nios II custom instruction provided + by Altera and which can be enabled in QSYS builder. This accelerates + endian conversions in the kernel (e.g. ntohs). + +config NIOS2_CI_SWAB_NO + int "Byteswap custom instruction number" if NIOS2_CI_SWAB_SUPPORT + default 0 + help + Number of the instruction as configured in QSYS Builder. + +comment "Cache settings" + +config CUSTOM_CACHE_SETTINGS + bool "Custom cache settings" + help + This option allows you to tweak the cache settings used during early + boot (where the information from device tree is not yet available). + There should be no reason to change these values. Linux will work + perfectly fine, even if the Nios II is configured with smaller caches. + + Say N here unless you know what you are doing. + +config NIOS2_DCACHE_SIZE + hex "D-Cache size" if CUSTOM_CACHE_SETTINGS + range 0x200 0x10000 + default "0x800" + help + Maximum possible data cache size. + +config NIOS2_DCACHE_LINE_SIZE + hex "D-Cache line size" if CUSTOM_CACHE_SETTINGS + range 0x10 0x20 + default "0x20" + help + Minimum possible data cache line size. + +config NIOS2_ICACHE_SIZE + hex "I-Cache size" if CUSTOM_CACHE_SETTINGS + range 0x200 0x10000 + default "0x1000" + help + Maximum possible instruction cache size. + +endmenu diff --git a/arch/nios2/platform/Makefile b/arch/nios2/platform/Makefile new file mode 100644 index 000000000000..46364f1d9352 --- /dev/null +++ b/arch/nios2/platform/Makefile @@ -0,0 +1 @@ +obj-y += platform.o diff --git a/arch/nios2/platform/platform.c b/arch/nios2/platform/platform.c new file mode 100644 index 000000000000..d478773f758a --- /dev/null +++ b/arch/nios2/platform/platform.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2013 Altera Corporation + * Copyright (C) 2011 Thomas Chou + * Copyright (C) 2011 Walter Goossens + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file COPYING in the main directory of this + * archive for more details. + */ + +#include <linux/init.h> +#include <linux/of_platform.h> +#include <linux/of_address.h> +#include <linux/of_fdt.h> +#include <linux/err.h> +#include <linux/slab.h> +#include <linux/sys_soc.h> +#include <linux/io.h> + +static int __init nios2_soc_device_init(void) +{ + struct soc_device *soc_dev; + struct soc_device_attribute *soc_dev_attr; + const char *machine; + + soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); + if (soc_dev_attr) { + machine = of_flat_dt_get_machine_name(); + if (machine) + soc_dev_attr->machine = kasprintf(GFP_KERNEL, "%s", + machine); + + soc_dev_attr->family = "Nios II"; + + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR(soc_dev)) { + kfree(soc_dev_attr->machine); + kfree(soc_dev_attr); + } + } + + return of_platform_populate(NULL, of_default_bus_match_table, + NULL, NULL); +} + +device_initcall(nios2_soc_device_init); |