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authorAlan Kao <alankao@andestech.com>2022-03-02 10:42:45 +0300
committerArnd Bergmann <arnd@arndb.de>2022-03-07 15:54:59 +0300
commitaec499c75cf8e0b599be4d559e6922b613085f8f (patch)
treeeadb9cd597d33c8c2f928dbd41e73b73f0b49398 /arch/nds32/include/asm/highmem.h
parentdd865f090f0382ba9e74dc4fe1008c08a67a6fca (diff)
downloadlinux-aec499c75cf8e0b599be4d559e6922b613085f8f.tar.xz
nds32: Remove the architecture
The nds32 architecture, also known as AndeStar V3, is a custom 32-bit RISC target designed by Andes Technologies. Support was added to the kernel in 2016 as the replacement RISC-V based V5 processors were already announced, and maintained by (current or former) Andes employees. As explained by Alan Kao, new customers are now all using RISC-V, and all known nds32 users are already on longterm stable kernels provided by Andes, with no development work going into mainline support any more. While the port is still in a reasonably good shape, it only gets worse over time without active maintainers, so it seems best to remove it before it becomes unusable. As always, if it turns out that there are mainline users after all, and they volunteer to maintain the port in the future, the removal can be reverted. Link: https://lore.kernel.org/linux-mm/YhdWNLUhk+x9RAzU@yamatobi.andestech.com/ Link: https://lore.kernel.org/lkml/20220302065213.82702-1-alankao@andestech.com/ Link: https://www.andestech.com/en/products-solutions/andestar-architecture/ Signed-off-by: Alan Kao <alankao@andestech.com> [arnd: rewrite changelog to provide more background] Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/nds32/include/asm/highmem.h')
-rw-r--r--arch/nds32/include/asm/highmem.h65
1 files changed, 0 insertions, 65 deletions
diff --git a/arch/nds32/include/asm/highmem.h b/arch/nds32/include/asm/highmem.h
deleted file mode 100644
index 16159a8716f2..000000000000
--- a/arch/nds32/include/asm/highmem.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-// Copyright (C) 2005-2017 Andes Technology Corporation
-
-#ifndef _ASM_HIGHMEM_H
-#define _ASM_HIGHMEM_H
-
-#include <asm/proc-fns.h>
-#include <asm/fixmap.h>
-
-/*
- * Right now we initialize only a single pte table. It can be extended
- * easily, subsequent pte tables have to be allocated in one physical
- * chunk of RAM.
- */
-/*
- * Ordering is (from lower to higher memory addresses):
- *
- * high_memory
- * Persistent kmap area
- * PKMAP_BASE
- * fixed_addresses
- * FIXADDR_START
- * FIXADDR_TOP
- * Vmalloc area
- * VMALLOC_START
- * VMALLOC_END
- */
-#define PKMAP_BASE ((FIXADDR_START - PGDIR_SIZE) & (PGDIR_MASK))
-#define LAST_PKMAP PTRS_PER_PTE
-#define LAST_PKMAP_MASK (LAST_PKMAP - 1)
-#define PKMAP_NR(virt) (((virt) - (PKMAP_BASE)) >> PAGE_SHIFT)
-#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
-
-static inline void flush_cache_kmaps(void)
-{
- cpu_dcache_wbinval_all();
-}
-
-/* declarations for highmem.c */
-extern unsigned long highstart_pfn, highend_pfn;
-
-extern pte_t *pkmap_page_table;
-
-extern void kmap_init(void);
-
-/*
- * FIXME: The below looks broken vs. a kmap_atomic() in task context which
- * is interupted and another kmap_atomic() happens in interrupt context.
- * But what do I know about nds32. -- tglx
- */
-#define arch_kmap_local_post_map(vaddr, pteval) \
- do { \
- __nds32__tlbop_inv(vaddr); \
- __nds32__mtsr_dsb(vaddr, NDS32_SR_TLB_VPN); \
- __nds32__tlbop_rwr(pteval); \
- __nds32__isb(); \
- } while (0)
-
-#define arch_kmap_local_pre_unmap(vaddr) \
- do { \
- __nds32__tlbop_inv(vaddr); \
- __nds32__isb(); \
- } while (0)
-
-#endif