diff options
| author | John Crispin <blogic@openwrt.org> | 2015-11-04 13:50:06 +0300 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-11-11 10:37:54 +0300 |
| commit | 81857db913e9782546d29b52cd3efc80c0145c23 (patch) | |
| tree | dc2f0850c96bf7416bcbc2ceb890c60c7c8a3167 /arch/mips | |
| parent | 1b04be20f6e38672d81f2de844488164bca988ca (diff) | |
| download | linux-81857db913e9782546d29b52cd3efc80c0145c23.tar.xz | |
MIPS: ralink: Add support for mt7688
MT7688 is similar tot he MT7628 but has a different wifi radio.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11439/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/include/asm/mach-ralink/mt7620.h | 1 | ||||
| -rw-r--r-- | arch/mips/ralink/mt7620.c | 35 |
2 files changed, 30 insertions, 6 deletions
diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h index 1976fb815fd1..590681af4bed 100644 --- a/arch/mips/include/asm/mach-ralink/mt7620.h +++ b/arch/mips/include/asm/mach-ralink/mt7620.h @@ -24,6 +24,7 @@ enum mt762x_soc_type { #define SYSC_REG_CHIP_NAME0 0x00 #define SYSC_REG_CHIP_NAME1 0x04 +#define SYSC_REG_EFUSE_CFG 0x08 #define SYSC_REG_CHIP_REV 0x0c #define SYSC_REG_SYSTEM_CONFIG0 0x10 #define SYSC_REG_SYSTEM_CONFIG1 0x14 diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index 2ea5ff6dc22e..4d1a0339dd54 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -40,6 +40,12 @@ /* is this a MT7620 or a MT7628 */ enum mt762x_soc_type mt762x_soc; +/* EFUSE bits */ +#define EFUSE_MT7688 0x100000 + +/* DRAM type bit */ +#define DRAM_TYPE_MT7628_MASK 0x1 + /* does the board have sdram or ddram */ static int dram_type; @@ -227,6 +233,12 @@ static struct rt2880_pmx_group mt7628an_pinmux_data[] = { { 0 } }; +static inline int is_mt76x8(void) +{ + return mt762x_soc == MT762X_SOC_MT7628AN || + mt762x_soc == MT762X_SOC_MT7688; +} + static __init u32 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) { @@ -381,7 +393,7 @@ void __init ralink_clk_init(void) #define RINT(x) ((x) / 1000000) #define RFRAC(x) (((x) / 1000) % 1000) - if (mt762x_soc == MT762X_SOC_MT7628AN) { + if (is_mt76x8()) { if (xtal_rate == MHZ(40)) cpu_rate = MHZ(580); else @@ -511,8 +523,15 @@ void prom_soc_init(struct ralink_soc_info *soc_info) #endif } } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) { - mt762x_soc = MT762X_SOC_MT7628AN; - name = "MT7628AN"; + u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG); + + if (efuse & EFUSE_MT7688) { + mt762x_soc = MT762X_SOC_MT7688; + name = "MT7688"; + } else { + mt762x_soc = MT762X_SOC_MT7628AN; + name = "MT7628AN"; + } soc_info->compatible = "ralink,mt7628an-soc"; } else { panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); @@ -525,10 +544,14 @@ void prom_soc_init(struct ralink_soc_info *soc_info) (rev & CHIP_REV_ECO_MASK)); cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0); - dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK; + if (is_mt76x8()) + dram_type = cfg0 & DRAM_TYPE_MT7628_MASK; + else + dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & + SYSCFG0_DRAM_TYPE_MASK; soc_info->mem_base = MT7620_DRAM_BASE; - if (mt762x_soc == MT762X_SOC_MT7628AN) + if (is_mt76x8()) mt7628_dram_init(soc_info); else mt7620_dram_init(soc_info); @@ -541,7 +564,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info) pr_info("Digital PMU set to %s control\n", (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw")); - if (mt762x_soc == MT762X_SOC_MT7628AN) + if (is_mt76x8()) rt2880_pinmux_data = mt7628an_pinmux_data; else rt2880_pinmux_data = mt7620a_pinmux_data; |