diff options
| author | Len Brown <len.brown@intel.com> | 2005-09-08 09:45:47 +0400 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2005-09-08 09:45:47 +0400 |
| commit | 64e47488c913ac704d465a6af86a26786d1412a5 (patch) | |
| tree | d3b0148592963dcde26e4bb35ddfec8b1eaf8e23 /arch/mips | |
| parent | 4a35a46bf1cda4737c428380d1db5d15e2590d18 (diff) | |
| parent | caf39e87cc1182f7dae84eefc43ca14d54c78ef9 (diff) | |
| download | linux-64e47488c913ac704d465a6af86a26786d1412a5.tar.xz | |
Merge linux-2.6 with linux-acpi-2.6
Diffstat (limited to 'arch/mips')
195 files changed, 1266 insertions, 1999 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 898de2df1fc7..8d76eb1ff291 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -4,27 +4,52 @@ config MIPS # Horrible source of confusion. Die, die, die ... select EMBEDDED -config MIPS64 - bool "64-bit kernel" - help - Select this option if you want to build a 64-bit kernel. You should - only select this option if you have hardware that actually has a - 64-bit processor and if your application will actually benefit from - 64-bit processing, otherwise say N. You must say Y for kernels for - SGI IP27 (Origin 200 and 2000) and SGI IP32 (O2). If in doubt say N. - -config 64BIT - def_bool MIPS64 - -config MIPS32 +# shouldn't it be per-subarchitecture? +config ARCH_MAY_HAVE_PC_FDC bool - depends on MIPS64 = 'n' default y mainmenu "Linux/MIPS Kernel Configuration" source "init/Kconfig" +config SYS_SUPPORTS_32BIT_KERNEL + bool +config SYS_SUPPORTS_64BIT_KERNEL + bool +config CPU_SUPPORTS_32BIT_KERNEL + bool +config CPU_SUPPORTS_64BIT_KERNEL + bool + +menu "Kernel type" + +choice + + prompt "Kernel code model" + help + You should only select this option if you have a workload that + actually benefits from 64-bit processing or if your machine has + large memory. You will only be presented a single option in this + menu if your system does not support both 32-bit and 64-bit kernels. + +config 32BIT + bool "32-bit kernel" + depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL + select TRAD_SIGNALS + help + Select this option if you want to build a 32-bit kernel. + +config 64BIT + bool "64-bit kernel" + depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL + help + Select this option if you want to build a 64-bit kernel. + +endchoice + +endmenu + menu "Machine selection" config MACH_JAZZ @@ -34,6 +59,8 @@ config MACH_JAZZ select GENERIC_ISA_DMA select I8259 select ISA + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL help This a family of machines based on the MIPS R4030 chipset which was used by several vendors to build RISC/os and Windows NT workstations. @@ -71,7 +98,9 @@ config OLIVETTI_M700 <http://www.linux-mips.org/>. config MACH_VR41XX - bool "Support for NEC VR41XX-based machines" + bool "Support for NEC VR4100 series based machines" + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL config NEC_CMBVR4133 bool "Support for NEC CMB-VR4133" @@ -80,7 +109,6 @@ config NEC_CMBVR4133 select DMA_NONCOHERENT select IRQ_CPU select HW_HAS_PCI - select PCI_VR41XX config ROCKHOPPER bool "Support for Rockhopper baseboard" @@ -91,6 +119,7 @@ config ROCKHOPPER config CASIO_E55 bool "Support for CASIO CASSIOPEIA E-10/15/55/65" depends on MACH_VR41XX + select CPU_LITTLE_ENDIAN select DMA_NONCOHERENT select IRQ_CPU select ISA @@ -98,53 +127,54 @@ config CASIO_E55 config IBM_WORKPAD bool "Support for IBM WorkPad z50" depends on MACH_VR41XX + select CPU_LITTLE_ENDIAN select DMA_NONCOHERENT select IRQ_CPU select ISA -config TANBAC_TB0226 - bool "Support for TANBAC TB0226 (Mbase)" +config TANBAC_TB022X + bool "Support for TANBAC VR4131 multichip module and TANBAC VR4131DIMM" depends on MACH_VR41XX + select CPU_LITTLE_ENDIAN select DMA_NONCOHERENT - select HW_HAS_PCI select IRQ_CPU + select HW_HAS_PCI help - The TANBAC TB0226 (Mbase) is a MIPS-based platform manufactured by TANBAC. - Please refer to <http://www.tanbac.co.jp/> about Mbase. + The TANBAC VR4131 multichip module(TB0225) and + the TANBAC VR4131DIMM(TB0229) are MIPS-based platforms + manufactured by TANBAC. + Please refer to <http://www.tanbac.co.jp/> + about VR4131 multichip module and VR4131DIMM. -config TANBAC_TB0229 - bool "Support for TANBAC TB0229 (VR4131DIMM)" - depends on MACH_VR41XX - select DMA_NONCOHERENT - select HW_HAS_PCI - select IRQ_CPU +config TANBAC_TB0226 + bool "Support for TANBAC Mbase(TB0226)" + depends on TANBAC_TB022X + select GPIO_VR41XX help - The TANBAC TB0229 (VR4131DIMM) is a MIPS-based platform manufactured by TANBAC. - Please refer to <http://www.tanbac.co.jp/> about VR4131DIMM. + The TANBAC Mbase(TB0226) is a MIPS-based platform manufactured by TANBAC. + Please refer to <http://www.tanbac.co.jp/> about Mbase. config VICTOR_MPC30X bool "Support for Victor MP-C303/304" + depends on MACH_VR41XX + select CPU_LITTLE_ENDIAN select DMA_NONCOHERENT - select HW_HAS_PCI select IRQ_CPU - depends on MACH_VR41XX + select HW_HAS_PCI config ZAO_CAPCELLA bool "Support for ZAO Networks Capcella" depends on MACH_VR41XX + select CPU_LITTLE_ENDIAN select DMA_NONCOHERENT - select HW_HAS_PCI select IRQ_CPU + select HW_HAS_PCI config PCI_VR41XX bool "Add PCI control unit support of NEC VR4100 series" - depends on MACH_VR41XX && PCI - -config VRC4171 - tristate "Add NEC VRC4171 companion chip support" - depends on MACH_VR41XX && ISA - ---help--- - The NEC VRC4171/4171A is a companion chip for NEC VR4111/VR4121. + depends on MACH_VR41XX && HW_HAS_PCI + default y + select PCI config VRC4173 tristate "Add NEC VRC4173 companion chip support" @@ -154,25 +184,28 @@ config VRC4173 config TOSHIBA_JMR3927 bool "Support for Toshiba JMR-TX3927 board" - depends on MIPS32 select DMA_NONCOHERENT select HW_HAS_PCI select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL config MIPS_COBALT - bool "Support for Cobalt Server (EXPERIMENTAL)" + bool "Support for Cobalt Server" depends on EXPERIMENTAL select DMA_NONCOHERENT select HW_HAS_PCI select I8259 select IRQ_CPU + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL config MACH_DECSTATION bool "Support for DECstations" select BOOT_ELF32 select DMA_NONCOHERENT select IRQ_CPU - depends on MIPS32 || EXPERIMENTAL + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL ---help--- This enables support for DEC's MIPS based workstations. For details see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the @@ -194,6 +227,8 @@ config MIPS_EV64120 select DMA_NONCOHERENT select HW_HAS_PCI select MIPS_GT64120 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help This is an evaluation board based on the Galileo GT-64120 single-chip system controller that contains a MIPS R5000 compatible @@ -214,6 +249,8 @@ config MIPS_EV96100 select MIPS_GT96100 select RM7000_CPU_SCACHE select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help This is an evaluation board based on the Galileo GT-96100 LAN/WAN communications controllers containing a MIPS R5000 compatible core @@ -224,6 +261,8 @@ config MIPS_IVR bool "Support for Globespan IVR board" select DMA_NONCOHERENT select HW_HAS_PCI + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL help This is an evaluation board built by Globespan to showcase thir iVR (Internet Video Recorder) design. It utilizes a QED RM5231 @@ -237,6 +276,8 @@ config LASAT select HW_HAS_PCI select MIPS_GT64120 select R5000_CPU_SCACHE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL config PICVUE tristate "PICVUE LCD display driver" @@ -258,6 +299,8 @@ config MIPS_ITE8172 bool "Support for ITE 8172G board" select DMA_NONCOHERENT select HW_HAS_PCI + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL help Ths is an evaluation board made by ITE <http://www.ite.com.tw/> with ATX form factor that utilizes a MIPS R5000 to work with its @@ -281,6 +324,8 @@ config MIPS_ATLAS select HW_HAS_PCI select MIPS_GT64120 select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help This enables support for the QED R5231-based MIPS Atlas evaluation board. @@ -295,6 +340,8 @@ config MIPS_MALTA select I8259 select MIPS_GT64120 select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help This enables support for the VR5000-based MIPS Malta evaluation board. @@ -304,6 +351,8 @@ config MIPS_SEAD depends on EXPERIMENTAL select IRQ_CPU select DMA_NONCOHERENT + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL config MOMENCO_OCELOT bool "Support for Momentum Ocelot board" @@ -314,6 +363,8 @@ config MOMENCO_OCELOT select MIPS_GT64120 select RM7000_CPU_SCACHE select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help The Ocelot is a MIPS-based Single Board Computer (SBC) made by Momentum Computer <http://www.momenco.com/>. @@ -327,6 +378,8 @@ config MOMENCO_OCELOT_G select PCI_MARVELL select RM7000_CPU_SCACHE select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help The Ocelot is a MIPS-based Single Board Computer (SBC) made by Momentum Computer <http://www.momenco.com/>. @@ -340,6 +393,8 @@ config MOMENCO_OCELOT_C select PCI_MARVELL select RM7000_CPU_SCACHE select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help The Ocelot is a MIPS-based Single Board Computer (SBC) made by Momentum Computer <http://www.momenco.com/>. @@ -355,6 +410,8 @@ config MOMENCO_OCELOT_3 select PCI_MARVELL select RM7000_CPU_SCACHE select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help The Ocelot-3 is based off Discovery III System Controller and PMC-Sierra Rm79000 core. @@ -371,6 +428,8 @@ config MOMENCO_JAGUAR_ATX select PCI_MARVELL select RM7000_CPU_SCACHE select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help The Jaguar ATX is a MIPS-based Single Board Computer (SBC) made by Momentum Computer <http://www.momenco.com/>. @@ -390,6 +449,8 @@ config PMC_YOSEMITE select IRQ_CPU_RM7K select IRQ_CPU_RM9K select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help Yosemite is an evaluation board for the RM9000x2 processor manufactured by PMC-Sierra @@ -407,6 +468,8 @@ config DDB5074 select IRQ_CPU select I8259 select ISA + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help This enables support for the VR5000-based NEC DDB Vrc-5074 evaluation board. @@ -419,6 +482,8 @@ config DDB5476 select IRQ_CPU select I8259 select ISA + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL help This enables support for the R5432-based NEC DDB Vrc-5476 evaluation board. @@ -433,6 +498,8 @@ config DDB5477 select HW_HAS_PCI select I8259 select IRQ_CPU + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL help This enables support for the R5432-based NEC DDB Vrc-5477, or Rockhopper/SolutionGear boards with R5432/R5500 CPUs. @@ -445,10 +512,23 @@ config DDB5477_BUS_FREQUENCY depends on DDB5477 default 0 -config NEC_OSPREY - bool "Support for NEC Osprey board" - select DMA_NONCOHERENT - select IRQ_CPU +config QEMU + bool "Support for Qemu" + select DMA_COHERENT + select GENERIC_ISA_DMA + select HAVE_STD_PC_SERIAL_PORT + select I8259 + select ISA + select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + help + Qemu is a software emulator which among other architectures also + can simulate a MIPS32 4Kc system. This patch adds support for the + system architecture that currently is being simulated by Qemu. It + will eventually be removed again when Qemu has the capability to + simulate actual MIPS hardware platforms. More information on Qemu + can be found at http://www.linux-mips.org/wiki/Qemu. config SGI_IP22 bool "Support for SGI IP22 (Indy/Indigo2)" @@ -459,6 +539,8 @@ config SGI_IP22 select IP22_CPU_SCACHE select IRQ_CPU select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help This are the SGI Indy, Challenge S and Indigo2, as well as certain OEM variants like the Tandem CMN B006S. To compile a Linux kernel @@ -466,12 +548,12 @@ config SGI_IP22 config SGI_IP27 bool "Support for SGI IP27 (Origin200/2000)" - depends on MIPS64 select ARC select ARC64 select DMA_IP27 select HW_HAS_PCI select PCI_DOMAINS + select SYS_SUPPORTS_64BIT_KERNEL help This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics workstations. To compile a Linux kernel that runs on these, say Y @@ -534,7 +616,7 @@ config REPLICATE_EXHANDLERS config SGI_IP32 bool "Support for SGI IP32 (O2) (EXPERIMENTAL)" - depends on MIPS64 && EXPERIMENTAL + depends on EXPERIMENTAL select ARC select ARC32 select BOOT_ELF32 @@ -544,12 +626,13 @@ config SGI_IP32 select HW_HAS_PCI select R5000_CPU_SCACHE select RM7000_CPU_SCACHE + select SYS_SUPPORTS_64BIT_KERNEL help If you want this kernel to run on SGI O2 workstation, say Y here. config SOC_AU1X00 - depends on MIPS32 bool "Support for AMD/Alchemy Au1X00 SOCs" + select SYS_SUPPORTS_32BIT_KERNEL choice prompt "Au1X00 SOC Type" @@ -661,6 +744,8 @@ config SIBYTE_SB1xxx_SOC select BOOT_ELF32 select DMA_COHERENT select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL choice prompt "BCM1xxx SOC-based board" @@ -880,6 +965,8 @@ config SNI_RM200_PCI select HW_HAS_PCI select I8259 select ISA + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL help The SNI RM200 PCI was a MIPS-based platform manufactured by Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid @@ -888,13 +975,14 @@ config SNI_RM200_PCI config TOSHIBA_RBTX4927 bool "Support for Toshiba TBTX49[23]7 board" - depends on MIPS32 select DMA_NONCOHERENT select HAS_TXX9_SERIAL select HW_HAS_PCI select I8259 select ISA select SWAP_IO_SPACE + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL help This Toshiba board is based on the TX4927 processor. Say Y here to support this machine type @@ -926,13 +1014,21 @@ config ARC depends on SNI_RM200_PCI || SGI_IP32 || SGI_IP27 || SGI_IP22 || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61 default y -config DMA_COHERENT +config DMA_COHERENT + bool + +config DMA_IP27 bool -config DMA_IP27 +config DMA_IP32 bool + select DMA_NEED_PCI_MAP_STATE -config DMA_NONCOHERENT +config DMA_NONCOHERENT + bool + select DMA_NEED_PCI_MAP_STATE + +config DMA_NEED_PCI_MAP_STATE bool config EARLY_PRINTK @@ -974,7 +1070,7 @@ config MIPS_DISABLE_OBSOLETE_IDE config CPU_LITTLE_ENDIAN bool "Generate little endian code" - default y if ACER_PICA_61 || CASIO_E55 || DDB5074 || DDB5476 || DDB5477 || MACH_DECSTATION || IBM_WORKPAD || LASAT || MIPS_COBALT || MIPS_ITE8172 || MIPS_IVR || SOC_AU1X00 || NEC_OSPREY || OLIVETTI_M700 || SNI_RM200_PCI || VICTOR_MPC30X || ZAO_CAPCELLA + default y if ACER_PICA_61 || CASIO_E55 || DDB5074 || DDB5476 || DDB5477 || MACH_DECSTATION || IBM_WORKPAD || LASAT || MIPS_COBALT || MIPS_ITE8172 || MIPS_IVR || SOC_AU1X00 || OLIVETTI_M700 || SNI_RM200_PCI || VICTOR_MPC30X || ZAO_CAPCELLA default n if MIPS_EV64120 || MIPS_EV96100 || MOMENCO_OCELOT || MOMENCO_OCELOT_G || SGI_IP22 || SGI_IP27 || SGI_IP32 || TOSHIBA_JMR3927 help Some MIPS machines can be configured for either little or big endian @@ -1091,11 +1187,6 @@ config ARC32 config HAVE_STD_PC_SERIAL_PORT bool -config VR4181 - bool - depends on NEC_OSPREY - default y - config ARC_CONSOLE bool "ARC console support" depends on SGI_IP22 || SNI_RM200_PCI @@ -1145,13 +1236,16 @@ choice config CPU_MIPS32 bool "MIPS32" + select CPU_SUPPORTS_32BIT_KERNEL config CPU_MIPS64 bool "MIPS64" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL config CPU_R3000 bool "R3000" - depends on MIPS32 + select CPU_SUPPORTS_32BIT_KERNEL help Please make sure to pick the right CPU type. Linux/MIPS is not designed to be generic, i.e. Kernels compiled for R3000 CPUs will @@ -1162,10 +1256,12 @@ config CPU_R3000 config CPU_TX39XX bool "R39XX" - depends on MIPS32 + select CPU_SUPPORTS_32BIT_KERNEL config CPU_VR41XX bool "R41xx" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL help The options selects support for the NEC VR41xx series of processors. Only choose this option if you have one of these processors as a @@ -1174,20 +1270,28 @@ config CPU_VR41XX config CPU_R4300 bool "R4300" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL help MIPS Technologies R4300-series processors. config CPU_R4X00 bool "R4x00" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL help MIPS Technologies R4000-series processors other than 4300, including the R4000, R4400, R4600, and 4700. config CPU_TX49XX bool "R49XX" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL config CPU_R5000 bool "R5000" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL help MIPS Technologies R5000-series processors other than the Nevada. @@ -1196,36 +1300,48 @@ config CPU_R5432 config CPU_R6000 bool "R6000" - depends on MIPS32 && EXPERIMENTAL + depends on EXPERIMENTAL + select CPU_SUPPORTS_32BIT_KERNEL help MIPS Technologies R6000 and R6000A series processors. Note these processors are extremly rare and the support for them is incomplete. config CPU_NEVADA bool "RM52xx" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL help QED / PMC-Sierra RM52xx-series ("Nevada") processors. config CPU_R8000 bool "R8000" - depends on MIPS64 && EXPERIMENTAL + depends on EXPERIMENTAL + select CPU_SUPPORTS_64BIT_KERNEL help MIPS Technologies R8000 processors. Note these processors are uncommon and the support for them is incomplete. config CPU_R10000 bool "R10000" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL help MIPS Technologies R10000-series processors. config CPU_RM7000 bool "RM7000" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL config CPU_RM9000 bool "RM9000" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL config CPU_SB1 bool "SB1" + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL endchoice @@ -1321,11 +1437,11 @@ config SB1_PASS_2_1_WORKAROUNDS config 64BIT_PHYS_ADDR bool "Support for 64-bit physical address space" - depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && MIPS32 + depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && 32BIT config CPU_ADVANCED bool "Override CPU Options" - depends on MIPS32 + depends on 32BIT help Saying yes here allows you to select support for various features your CPU may or may not have. Most people should say N here. @@ -1379,7 +1495,7 @@ config CPU_HAS_SYNC # config HIGHMEM bool "High Memory Support" - depends on MIPS32 && (CPU_R3000 || CPU_SB1 || CPU_R7000 || CPU_RM9000 || CPU_R10000) && !(MACH_DECSTATION || MOMENCO_JAGUAR_ATX) + depends on 32BIT && (CPU_R3000 || CPU_SB1 || CPU_R7000 || CPU_RM9000 || CPU_R10000) && !(MACH_DECSTATION || MOMENCO_JAGUAR_ATX) config ARCH_FLATMEM_ENABLE def_bool y @@ -1439,7 +1555,7 @@ config RTC_DS1742 config MIPS_INSANE_LARGE bool "Support for large 64-bit configurations" - depends on CPU_R10000 && MIPS64 + depends on CPU_R10000 && 64BIT help MIPS R10000 does support a 44 bit / 16TB address space as opposed to previous 64-bit processors which only supported 40 bit / 1TB. If you @@ -1540,11 +1656,11 @@ source "fs/Kconfig.binfmt" config TRAD_SIGNALS bool - default y if MIPS32 + default y if 32BIT config BUILD_ELF64 bool "Use 64-bit ELF format for building" - depends on MIPS64 + depends on 64BIT help A 64-bit kernel is usually built using the 64-bit ELF binary object format as it's one that allows arbitrary 64-bit constructs. For @@ -1559,11 +1675,11 @@ config BUILD_ELF64 config BINFMT_IRIX bool "Include IRIX binary compatibility" - depends on !CPU_LITTLE_ENDIAN && MIPS32 && BROKEN + depends on !CPU_LITTLE_ENDIAN && 32BIT && BROKEN config MIPS32_COMPAT bool "Kernel support for Linux/MIPS 32-bit binary compatibility" - depends on MIPS64 + depends on 64BIT help Select this option if you want Linux/MIPS 32-bit binary compatibility. Since all software available for Linux/MIPS is diff --git a/arch/mips/Makefile b/arch/mips/Makefile index bc1c44274a58..b0fdaee8d8d9 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -37,12 +37,12 @@ else 64bit-emul = elf64btsmip endif -ifdef CONFIG_MIPS32 +ifdef CONFIG_32BIT gcc-abi = 32 tool-prefix = $(32bit-tool-prefix) UTS_MACHINE := mips endif -ifdef CONFIG_MIPS64 +ifdef CONFIG_64BIT gcc-abi = 64 tool-prefix = $(64bit-tool-prefix) UTS_MACHINE := mips64 @@ -63,7 +63,7 @@ ld-emul = $(32bit-emul) vmlinux-32 = vmlinux vmlinux-64 = vmlinux.64 -cflags-$(CONFIG_MIPS64) += $(call cc-option,-mno-explicit-relocs) +cflags-$(CONFIG_64BIT) += $(call cc-option,-mno-explicit-relocs) endif # @@ -177,7 +177,7 @@ cflags-$(CONFIG_CPU_MIPS64) += \ cflags-$(CONFIG_CPU_R5000) += \ $(call set_gccflags,r5000,mips4,r5000,mips4,mips2) \ - -Wa,--trap + -Wa,--trap cflags-$(CONFIG_CPU_R5432) += \ $(call set_gccflags,r5400,mips4,r5000,mips4,mips2) \ @@ -423,6 +423,12 @@ core-$(CONFIG_PMC_YOSEMITE) += arch/mips/pmc-sierra/yosemite/ cflags-$(CONFIG_PMC_YOSEMITE) += -Iinclude/asm-mips/mach-yosemite load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000 +# Qemu simulating MIPS32 4Kc +# +core-$(CONFIG_QEMU) += arch/mips/qemu/ +cflags-$(CONFIG_QEMU) += -Iinclude/asm-mips/mach-qemu +load-$(CONFIG_QEMU) += 0xffffffff80010000 + # # Momentum Ocelot-3 # @@ -469,13 +475,6 @@ cflags-$(CONFIG_LASAT) += -Iinclude/asm-mips/mach-lasat load-$(CONFIG_LASAT) += 0xffffffff80000000 # -# NEC Osprey (vr4181) board -# -core-$(CONFIG_NEC_OSPREY) += arch/mips/vr4181/common/ \ - arch/mips/vr4181/osprey/ -load-$(CONFIG_NEC_OSPREY) += 0xffffffff80002000 - -# # Common VR41xx # core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/ @@ -490,13 +489,11 @@ load-$(CONFIG_NEC_CMBVR4133) += 0xffffffff80100000 # # ZAO Networks Capcella (VR4131) # -core-$(CONFIG_ZAO_CAPCELLA) += arch/mips/vr41xx/zao-capcella/ load-$(CONFIG_ZAO_CAPCELLA) += 0xffffffff80000000 # # Victor MP-C303/304 (VR4122) # -core-$(CONFIG_VICTOR_MPC30X) += arch/mips/vr41xx/victor-mpc30x/ load-$(CONFIG_VICTOR_MPC30X) += 0xffffffff80001000 # @@ -512,16 +509,9 @@ core-$(CONFIG_CASIO_E55) += arch/mips/vr41xx/casio-e55/ load-$(CONFIG_CASIO_E55) += 0xffffffff80004000 # -# TANBAC TB0226 Mbase (VR4131) -# -core-$(CONFIG_TANBAC_TB0226) += arch/mips/vr41xx/tanbac-tb0226/ -load-$(CONFIG_TANBAC_TB0226) += 0xffffffff80000000 - -# -# TANBAC TB0229 VR4131DIMM (VR4131) +# TANBAC VR4131 multichip module(TB0225) and TANBAC VR4131DIMM(TB0229) (VR4131) # -core-$(CONFIG_TANBAC_TB0229) += arch/mips/vr41xx/tanbac-tb0229/ -load-$(CONFIG_TANBAC_TB0229) += 0xffffffff80000000 +load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000 # # SGI IP22 (Indy/Indigo2) @@ -534,10 +524,10 @@ load-$(CONFIG_TANBAC_TB0229) += 0xffffffff80000000 # core-$(CONFIG_SGI_IP22) += arch/mips/sgi-ip22/ cflags-$(CONFIG_SGI_IP22) += -Iinclude/asm-mips/mach-ip22 -ifdef CONFIG_MIPS32 +ifdef CONFIG_32BIT load-$(CONFIG_SGI_IP22) += 0xffffffff88002000 endif -ifdef CONFIG_MIPS64 +ifdef CONFIG_64BIT load-$(CONFIG_SGI_IP22) += 0xffffffff88004000 endif @@ -642,7 +632,7 @@ load-$(CONFIG_TOSHIBA_RBTX4927) += 0xffffffff80020000 cflags-y += -Iinclude/asm-mips/mach-generic drivers-$(CONFIG_PCI) += arch/mips/pci/ -ifdef CONFIG_MIPS32 +ifdef CONFIG_32BIT ifdef CONFIG_CPU_LITTLE_ENDIAN JIFFIES = jiffies_64 else @@ -674,8 +664,8 @@ CPPFLAGS_vmlinux.lds := \ head-y := arch/mips/kernel/head.o arch/mips/kernel/init_task.o libs-y += arch/mips/lib/ -libs-$(CONFIG_MIPS32) += arch/mips/lib-32/ -libs-$(CONFIG_MIPS64) += arch/mips/lib-64/ +libs-$(CONFIG_32BIT) += arch/mips/lib-32/ +libs-$(CONFIG_64BIT) += arch/mips/lib-64/ core-y += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/ @@ -683,7 +673,7 @@ drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/ ifdef CONFIG_LASAT rom.bin rom.sw: vmlinux - $(call descend,arch/mips/lasat/image,$@) + $(Q)$(MAKE) $(build)=arch/mips/lasat/image $@ endif # @@ -730,7 +720,7 @@ archclean: @$(MAKE) $(clean)=arch/mips/boot @$(MAKE) $(clean)=arch/mips/lasat -# Generate <asm/offset.h +# Generate <asm/offset.h # # The default rule is suffering from funny problems on MIPS so we using our # own ... diff --git a/arch/mips/au1000/common/pci.c b/arch/mips/au1000/common/pci.c index 533721eef6ae..4e5a6e1a9a6e 100644 --- a/arch/mips/au1000/common/pci.c +++ b/arch/mips/au1000/common/pci.c @@ -40,14 +40,14 @@ /* TBD */ static struct resource pci_io_resource = { - "pci IO space", + "pci IO space", (u32)PCI_IO_START, (u32)PCI_IO_END, IORESOURCE_IO }; static struct resource pci_mem_resource = { - "pci memory space", + "pci memory space", (u32)PCI_MEM_START, (u32)PCI_MEM_END, IORESOURCE_MEM @@ -68,7 +68,7 @@ static unsigned long virt_io_addr; static int __init au1x_pci_setup(void) { #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) - virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START, + virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START, Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1); if (!virt_io_addr) { @@ -77,7 +77,7 @@ static int __init au1x_pci_setup(void) } #ifdef CONFIG_DMA_NONCOHERENT - /* + /* * Set the NC bit in controller for Au1500 pre-AC silicon */ u32 prid = read_c0_prid(); diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c index dbc8b1bda963..eff89e109ce6 100644 --- a/arch/mips/au1000/common/setup.c +++ b/arch/mips/au1000/common/setup.c @@ -97,7 +97,7 @@ static int __init au1x00_setup(void) argptr = prom_getcmdline(); strcat(argptr, " console=ttyS0,115200"); } -#endif +#endif #ifdef CONFIG_FB_AU1100 if ((argptr = strstr(argptr, "video=")) == NULL) { diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c index fe418f1620c3..57675b41480e 100644 --- a/arch/mips/au1000/common/time.c +++ b/arch/mips/au1000/common/time.c @@ -281,7 +281,7 @@ unsigned long cal_r4koff(void) cpu_speed = count * 2; } #else - cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * + cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; count = cpu_speed / 2; #endif @@ -356,7 +356,7 @@ static unsigned long do_fast_cp0_gettimeoffset(void) : "hi", "lo", GCC_REG_ACCUM); /* - * Due to possible jiffies inconsistencies, we need to check + * Due to possible jiffies inconsistencies, we need to check * the result so that we'll get a timer that is monotonic. */ if (res >= USECS_PER_JIFFY) @@ -375,8 +375,8 @@ static unsigned long do_fast_pm_gettimeoffset(void) au_sync(); offset = pc0 - last_pc0; if (offset > 2*MATCH20_INC) { - printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n", - (unsigned)offset, (unsigned)last_pc0, + printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n", + (unsigned)offset, (unsigned)last_pc0, (unsigned)last_match20, (unsigned)pc0); } offset = (unsigned long)((offset * 305) / 10); @@ -394,11 +394,11 @@ void au1xxx_timer_setup(struct irqaction *irq) r4k_offset = cal_r4koff(); printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset); - //est_freq = 2*r4k_offset*HZ; - est_freq = r4k_offset*HZ; + //est_freq = 2*r4k_offset*HZ; + est_freq = r4k_offset*HZ; est_freq += 5000; /* round */ est_freq -= est_freq%10000; - printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, (est_freq%1000000)*100/1000000); set_au1x00_speed(est_freq); set_au1x00_lcd_clock(); // program the LCD clock diff --git a/arch/mips/au1000/csb250/board_setup.c b/arch/mips/au1000/csb250/board_setup.c index 90426eaffb23..1c55c5f59d75 100644 --- a/arch/mips/au1000/csb250/board_setup.c +++ b/arch/mips/au1000/csb250/board_setup.c @@ -182,7 +182,7 @@ void __init board_setup(void) au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV); au_writel(0, Au1500_PCI_MWBASE_REV_CCL); au_writel(0x02a00356, Au1500_PCI_STATCMD); - au_writel(0x00003c04, Au1500_PCI_HDRTYPE); + au_writel(0x00003c04, Au1500_PCI_HDRTYPE); au_writel(0x00000008, Au1500_PCI_MBAR); au_sync(); @@ -216,7 +216,7 @@ csb250_pci_idsel(unsigned int devsel, int assert) unsigned int gpio2_pins; retval = 1; - + /* First, disable both selects, then assert the one requested. */ au_writel(0xc000c000, GPIO2_OUTPUT); diff --git a/arch/mips/au1000/csb250/init.c b/arch/mips/au1000/csb250/init.c index 4320057fc439..bd99733abc0b 100644 --- a/arch/mips/au1000/csb250/init.c +++ b/arch/mips/au1000/csb250/init.c @@ -81,7 +81,7 @@ int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) csb_env[0] = env1; mips_machgroup = MACH_GROUP_ALCHEMY; - mips_machtype = MACH_CSB250; + mips_machtype = MACH_CSB250; prom_init_cmdline(); memsize_str = prom_getenv("memsize"); diff --git a/arch/mips/au1000/db1x00/init.c b/arch/mips/au1000/db1x00/init.c index 51eee94a5e82..4b9d5e46edbb 100644 --- a/arch/mips/au1000/db1x00/init.c +++ b/arch/mips/au1000/db1x00/init.c @@ -61,7 +61,7 @@ void __init prom_init(void) prom_envp = (char **) fw_arg2; mips_machgroup = MACH_GROUP_ALCHEMY; - mips_machtype = MACH_DB1000; /* set the platform # */ + mips_machtype = MACH_DB1000; /* set the platform # */ prom_init_cmdline(); diff --git a/arch/mips/au1000/hydrogen3/init.c b/arch/mips/au1000/hydrogen3/init.c index eee4adf98711..8cc9879dd582 100644 --- a/arch/mips/au1000/hydrogen3/init.c +++ b/arch/mips/au1000/hydrogen3/init.c @@ -63,7 +63,7 @@ int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) prom_envp = envp; mips_machgroup = MACH_GROUP_ALCHEMY; - mips_machtype = MACH_DB1000; /* set the platform # */ + mips_machtype = MACH_DB1000; /* set the platform # */ prom_init_cmdline(); memsize_str = prom_getenv("memsize"); diff --git a/arch/mips/au1000/pb1000/board_setup.c b/arch/mips/au1000/pb1000/board_setup.c index 2fa211b69329..0b4807dc9f44 100644 --- a/arch/mips/au1000/pb1000/board_setup.c +++ b/arch/mips/au1000/pb1000/board_setup.c @@ -174,7 +174,7 @@ void __init board_setup(void) case 0x02: /* HB */ break; default: /* HC and newer */ - /* Enable sys bus clock divider when IDLE state or no bus + /* Enable sys bus clock divider when IDLE state or no bus activity. */ au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); break; diff --git a/arch/mips/au1000/xxs1500/board_setup.c b/arch/mips/au1000/xxs1500/board_setup.c index 9dadc82536f4..1e59433dfd66 100644 --- a/arch/mips/au1000/xxs1500/board_setup.c +++ b/arch/mips/au1000/xxs1500/board_setup.c @@ -49,7 +49,7 @@ void board_reset (void) void __init board_setup(void) { u32 pin_func; - + // set multiple use pins (UART3/GPIO) to UART (it's used as UART too) pin_func = au_readl(SYS_PINFUNC) & (u32)(~SYS_PF_UR3); pin_func |= SYS_PF_UR3; @@ -75,11 +75,11 @@ void __init board_setup(void) au_writel(1, GPIO2_ENABLE); /* gpio2 208/9/10/11 are inputs */ au_writel((1<<8) | (1<<9) | (1<<10) | (1<<11), GPIO2_DIR); - + /* turn off power */ au_writel((au_readl(GPIO2_PINSTATE) & ~(1<<14))|(1<<30), GPIO2_OUTPUT); #endif - + #ifdef CONFIG_PCI #if defined(__MIPSEB__) diff --git a/arch/mips/au1000/xxs1500/init.c b/arch/mips/au1000/xxs1500/init.c index 03f755291b51..f1c76533b6fc 100644 --- a/arch/mips/au1000/xxs1500/init.c +++ b/arch/mips/au1000/xxs1500/init.c @@ -55,7 +55,7 @@ void __init prom_init(void) prom_envp = (char **) fw_arg2; mips_machgroup = MACH_GROUP_ALCHEMY; - mips_machtype = MACH_XXS1500; /* set the platform # */ + mips_machtype = MACH_XXS1500; /* set the platform # */ prom_init_cmdline(); diff --git a/arch/mips/au1000/xxs1500/irqmap.c b/arch/mips/au1000/xxs1500/irqmap.c index 954800a0ab52..52f2f7daeb05 100644 --- a/arch/mips/au1000/xxs1500/irqmap.c +++ b/arch/mips/au1000/xxs1500/irqmap.c @@ -56,7 +56,7 @@ au1xxx_irq_map_t au1xxx_irq_map[] = { { AU1500_GPIO_207, INTC_INT_LOW_LEVEL, 0 }, { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, - { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, + { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, { AU1000_GPIO_2, INTC_INT_LOW_LEVEL, 0 }, { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 }, { AU1000_GPIO_4, INTC_INT_LOW_LEVEL, 0 }, /* CF interrupt */ diff --git a/arch/mips/configs/atlas_defconfig b/arch/mips/configs/atlas_defconfig index caad7ca27abd..3120a02b8670 100644 --- a/arch/mips/configs/atlas_defconfig +++ b/arch/mips/configs/atlas_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:00 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -88,6 +88,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_MIPS_BONITO64=y CONFIG_MIPS_MSC=y # CONFIG_CPU_LITTLE_ENDIAN is not set diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig index 1b7f8a702d06..158e7165f4e3 100644 --- a/arch/mips/configs/capcella_defconfig +++ b/arch/mips/configs/capcella_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:00 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -97,6 +97,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig index 8861854561e5..4302c6f914f5 100644 --- a/arch/mips/configs/cobalt_defconfig +++ b/arch/mips/configs/cobalt_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:00 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -82,6 +82,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_I8259=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig index 19cac1bf4f01..962fc14b58c2 100644 --- a/arch/mips/configs/db1000_defconfig +++ b/arch/mips/configs/db1000_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:01 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -104,6 +104,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_MIPS_L1_CACHE_SHIFT=5 diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig index 035ac95d197e..6a528d479d70 100644 --- a/arch/mips/configs/db1100_defconfig +++ b/arch/mips/configs/db1100_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:01 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -104,6 +104,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_MIPS_L1_CACHE_SHIFT=5 diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig index c38c4ed18fe7..fed6f2fab48b 100644 --- a/arch/mips/configs/db1500_defconfig +++ b/arch/mips/configs/db1500_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:01 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig index ee81309ae3a5..178c0ad1af75 100644 --- a/arch/mips/configs/db1550_defconfig +++ b/arch/mips/configs/db1550_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:02 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/ddb5476_defconfig b/arch/mips/configs/ddb5476_defconfig index d43ed57c4b4e..70addc73f699 100644 --- a/arch/mips/configs/ddb5476_defconfig +++ b/arch/mips/configs/ddb5476_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:02 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -82,6 +82,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_I8259=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y diff --git a/arch/mips/configs/ddb5477_defconfig b/arch/mips/configs/ddb5477_defconfig index 5a032cdefd63..60292808b384 100644 --- a/arch/mips/configs/ddb5477_defconfig +++ b/arch/mips/configs/ddb5477_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:02 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -83,6 +83,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_I8259=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig index 32ada79da9d8..66ec1f41d122 100644 --- a/arch/mips/configs/decstation_defconfig +++ b/arch/mips/configs/decstation_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:03 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -88,6 +88,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_EARLY_PRINTK=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig index 52074a2085fb..ba2ec01defb1 100644 --- a/arch/mips/configs/e55_defconfig +++ b/arch/mips/configs/e55_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:03 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -96,6 +96,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 diff --git a/arch/mips/configs/ev64120_defconfig b/arch/mips/configs/ev64120_defconfig index 360e842fd4be..17e87f70f602 100644 --- a/arch/mips/configs/ev64120_defconfig +++ b/arch/mips/configs/ev64120_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:03 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -89,6 +89,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_MIPS_GT64120=y # CONFIG_SYSCLK_75 is not set diff --git a/arch/mips/configs/ev96100_defconfig b/arch/mips/configs/ev96100_defconfig index 657a9508d31a..9da4140eae00 100644 --- a/arch/mips/configs/ev96100_defconfig +++ b/arch/mips/configs/ev96100_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:03 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -88,6 +88,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_IRQ_CPU=y CONFIG_MIPS_GT64120=y diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig index 3fb102e6a7f7..17fa5c4e3ad1 100644 --- a/arch/mips/configs/ip22_defconfig +++ b/arch/mips/configs/ip22_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:04 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -90,6 +90,7 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_ARC=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_IRQ_CPU=y CONFIG_SWAP_IO_SPACE=y diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index b5bab3a42fc4..b2a67da1e031 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig @@ -4,7 +4,7 @@ # Wed Jan 26 02:49:04 2005 # CONFIG_MIPS=y -CONFIG_MIPS64=y +CONFIG_64BIT=y CONFIG_64BIT=y # diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig index bdf1415475ff..b26e1173365d 100644 --- a/arch/mips/configs/ip32_defconfig +++ b/arch/mips/configs/ip32_defconfig @@ -4,7 +4,7 @@ # Wed Jan 26 02:49:04 2005 # CONFIG_MIPS=y -CONFIG_MIPS64=y +CONFIG_64BIT=y CONFIG_64BIT=y # @@ -84,6 +84,7 @@ CONFIG_ARC=y CONFIG_DMA_IP32=y CONFIG_OWN_DMA=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_ARC32=y CONFIG_BOOT_ELF32=y diff --git a/arch/mips/configs/it8172_defconfig b/arch/mips/configs/it8172_defconfig index 1ca7746388f0..08bd3ad64761 100644 --- a/arch/mips/configs/it8172_defconfig +++ b/arch/mips/configs/it8172_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:05 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -90,6 +90,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_ITE_BOARD_GEN=y CONFIG_IT8172_CIR=y diff --git a/arch/mips/configs/ivr_defconfig b/arch/mips/configs/ivr_defconfig index c6eef708be1e..583ef5c5b1cd 100644 --- a/arch/mips/configs/ivr_defconfig +++ b/arch/mips/configs/ivr_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:05 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -89,6 +89,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_ITE_BOARD_GEN=y CONFIG_IT8172_CIR=y diff --git a/arch/mips/configs/jaguar-atx_defconfig b/arch/mips/configs/jaguar-atx_defconfig index 757c4e88cc00..8abb5a0c6c12 100644 --- a/arch/mips/configs/jaguar-atx_defconfig +++ b/arch/mips/configs/jaguar-atx_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:05 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -81,6 +81,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_LIMITED_DMA=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_IRQ_CPU=y diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig index e5a613906554..da5d9ee2ecce 100644 --- a/arch/mips/configs/jmr3927_defconfig +++ b/arch/mips/configs/jmr3927_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:06 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -82,6 +82,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_MIPS_TX3927=y CONFIG_SWAP_IO_SPACE=y diff --git a/arch/mips/configs/lasat200_defconfig b/arch/mips/configs/lasat200_defconfig index 1e7697834e90..8d600ae890f4 100644 --- a/arch/mips/configs/lasat200_defconfig +++ b/arch/mips/configs/lasat200_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:06 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -92,6 +92,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_MIPS_NILE4=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_MIPS_GT64120=y diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 61fb9fb97e6e..79519ac5af4a 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:53:14 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -88,6 +88,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_GENERIC_ISA_DMA=y CONFIG_I8259=y CONFIG_MIPS_BONITO64=y diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig index 31b8f2ad7338..0fea57ef18f2 100644 --- a/arch/mips/configs/mpc30x_defconfig +++ b/arch/mips/configs/mpc30x_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:07 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -97,6 +97,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 diff --git a/arch/mips/configs/ocelot_3_defconfig b/arch/mips/configs/ocelot_3_defconfig index 2cce682fffcf..b4cf97a732bc 100644 --- a/arch/mips/configs/ocelot_3_defconfig +++ b/arch/mips/configs/ocelot_3_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:07 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -89,6 +89,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_IRQ_CPU=y CONFIG_IRQ_CPU_RM7K=y diff --git a/arch/mips/configs/ocelot_c_defconfig b/arch/mips/configs/ocelot_c_defconfig index 0cbf48a62e02..a38903db85a0 100644 --- a/arch/mips/configs/ocelot_c_defconfig +++ b/arch/mips/configs/ocelot_c_defconfig @@ -4,7 +4,7 @@ # Wed Jan 26 02:49:07 2005 # CONFIG_MIPS=y -CONFIG_MIPS64=y +CONFIG_64BIT=y CONFIG_64BIT=y # @@ -80,6 +80,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_IRQ_CPU=y CONFIG_IRQ_MV64340=y diff --git a/arch/mips/configs/ocelot_defconfig b/arch/mips/configs/ocelot_defconfig index 4043950d360a..920d59b56a4e 100644 --- a/arch/mips/configs/ocelot_defconfig +++ b/arch/mips/configs/ocelot_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:08 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -82,6 +82,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_IRQ_CPU=y CONFIG_IRQ_CPU_RM7K=y diff --git a/arch/mips/configs/ocelot_g_defconfig b/arch/mips/configs/ocelot_g_defconfig index 3870af4537ad..ef5ea50893d1 100644 --- a/arch/mips/configs/ocelot_g_defconfig +++ b/arch/mips/configs/ocelot_g_defconfig @@ -4,7 +4,7 @@ # Wed Jan 26 02:49:08 2005 # CONFIG_MIPS=y -CONFIG_MIPS64=y +CONFIG_64BIT=y CONFIG_64BIT=y # @@ -80,6 +80,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_IRQ_CPU=y CONFIG_IRQ_CPU_RM7K=y diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig index 6cdabd550300..813e3a8b480b 100644 --- a/arch/mips/configs/pb1100_defconfig +++ b/arch/mips/configs/pb1100_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:08 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -104,6 +104,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SWAP_IO_SPACE=y # CONFIG_AU1X00_USB_DEVICE is not set diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig index 2aebbd2e82b3..49e528340a39 100644 --- a/arch/mips/configs/pb1500_defconfig +++ b/arch/mips/configs/pb1500_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:09 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig index 9e21edc28280..8e426776c098 100644 --- a/arch/mips/configs/pb1550_defconfig +++ b/arch/mips/configs/pb1550_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:09 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/osprey_defconfig b/arch/mips/configs/qemu_defconfig index 989cb9e7ae83..b6568e421b99 100644 --- a/arch/mips/configs/osprey_defconfig +++ b/arch/mips/configs/qemu_defconfig @@ -1,108 +1,133 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 02:49:08 2005 +# Linux kernel version: 2.6.13-rc6 +# Mon Aug 8 11:49:54 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set -# CONFIG_64BIT is not set -CONFIG_MIPS32=y # # Code maturity level options # -CONFIG_EXPERIMENTAL=y +# CONFIG_EXPERIMENTAL is not set CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup # CONFIG_LOCALVERSION="" -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set +# CONFIG_SWAP is not set +# CONFIG_SYSVIPC is not set # CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y +# CONFIG_SYSCTL is not set # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 # CONFIG_HOTPLUG is not set CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_FUTEX=y -CONFIG_EPOLL=y +CONFIG_PRINTK=y +# CONFIG_BUG is not set +# CONFIG_BASE_FULL is not set +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SHMEM=y +# CONFIG_SHMEM is not set CONFIG_CC_ALIGN_FUNCTIONS=0 CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 -# CONFIG_TINY_SHMEM is not set +CONFIG_TINY_SHMEM=y +CONFIG_BASE_SMALL=1 # # Loadable module support # -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_KMOD=y +# CONFIG_MODULES is not set # # Machine selection # -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_IVR is not set -# CONFIG_LASAT is not set # CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set # CONFIG_MOMENCO_OCELOT is not set -# CONFIG_MOMENCO_OCELOT_G is not set -# CONFIG_MOMENCO_OCELOT_C is not set # CONFIG_MOMENCO_OCELOT_3 is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set # CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set -CONFIG_NEC_OSPREY=y +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +CONFIG_QEMU=y # CONFIG_SGI_IP22 is not set -# CONFIG_SOC_AU1X00 is not set -# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set # CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_IRQ_CPU=y +CONFIG_DMA_COHERENT=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_I8259=y +CONFIG_CPU_BIG_ENDIAN=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SWAP_IO_SPACE=y CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_VR4181=y +CONFIG_HAVE_STD_PC_SERIAL_PORT=y # # CPU selection # -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set -CONFIG_CPU_VR41XX=y +# CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set +CONFIG_CPU_R4X00=y # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set @@ -113,17 +138,36 @@ CONFIG_CPU_VR41XX=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_MIPS_MT is not set +# CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y CONFIG_CPU_HAS_SYNC=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # +CONFIG_ISA=y CONFIG_MMU=y # @@ -132,10 +176,6 @@ CONFIG_MMU=y # CONFIG_PCCARD is not set # -# PC-card bridges -# - -# # PCI Hotplug Support # @@ -147,6 +187,56 @@ CONFIG_BINFMT_ELF=y CONFIG_TRAD_SIGNALS=y # +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_IP_TCPDIAG=y +# CONFIG_IP_TCPDIAG_IPV6 is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_BIC=y +# CONFIG_IPV6 is not set +# CONFIG_NETFILTER is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_NET_SCHED is not set +# CONFIG_NET_CLS_ROUTE is not set + +# +# Network testing +# +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set + +# # Device Drivers # @@ -154,7 +244,7 @@ CONFIG_TRAD_SIGNALS=y # Generic Driver Options # CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_FW_LOADER is not set # @@ -170,6 +260,7 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # # Plug and Play support # +# CONFIG_PNP is not set # # Block devices @@ -181,19 +272,16 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_BLK_DEV_RAM is not set CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_INITRAMFS_SOURCE="" -# CONFIG_LBD is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_CDROM_PKTCDVD is not set # # IO Schedulers # CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_ATA_OVER_ETH=m +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_ATA_OVER_ETH is not set # # ATA/ATAPI/MFM/RLL support @@ -206,6 +294,11 @@ CONFIG_ATA_OVER_ETH=m # CONFIG_SCSI is not set # +# Old CD-ROM drivers (not SCSI, not IDE) +# +# CONFIG_CD_NO_IDESCSI is not set + +# # Multi-device support (RAID and LVM) # # CONFIG_MD is not set @@ -213,6 +306,7 @@ CONFIG_ATA_OVER_ETH=m # # Fusion MPT device support # +# CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support @@ -223,84 +317,41 @@ CONFIG_ATA_OVER_ETH=m # # -# Networking support -# -CONFIG_NET=y - -# -# Networking options +# Network device support # -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK_DEV=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m -CONFIG_IP_TCPDIAG=m -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set -CONFIG_XFRM=y -CONFIG_XFRM_USER=m - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set +CONFIG_MII=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_SMC is not set +# CONFIG_NET_VENDOR_RACAL is not set +# CONFIG_DEPCA is not set +# CONFIG_HP100 is not set +CONFIG_NET_ISA=y +# CONFIG_E2100 is not set +# CONFIG_EWRK3 is not set +# CONFIG_EEXPRESS is not set +# CONFIG_EEXPRESS_PRO is not set +# CONFIG_HPLAN_PLUS is not set +# CONFIG_HPLAN is not set +# CONFIG_LP486E is not set +# CONFIG_ETH16I is not set +CONFIG_NE2000=y +# CONFIG_NET_PCI is not set +# CONFIG_NET_POCKET is not set # # Ethernet (1000 Mbit) @@ -313,6 +364,7 @@ CONFIG_NET_ETHERNET=y # # Token Ring devices # +# CONFIG_TR is not set # # Wireless LAN (non-hamradio) @@ -325,8 +377,8 @@ CONFIG_NET_ETHERNET=y # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set # # ISDN subsystem @@ -346,28 +398,13 @@ CONFIG_INPUT=y # # Userland interfaces # -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_JOYDEV is not set # CONFIG_INPUT_TSDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set # -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=m - -# # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set @@ -377,6 +414,12 @@ CONFIG_SERIO_RAW=m # CONFIG_INPUT_MISC is not set # +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# # Character devices # CONFIG_VT=y @@ -397,9 +440,8 @@ CONFIG_SERIAL_8250_NR_UARTS=4 # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_UNIX98_PTYS is not set +# CONFIG_LEGACY_PTYS is not set # # IPMI @@ -418,13 +460,17 @@ CONFIG_LEGACY_PTY_COUNT=256 # # Ftape, the floppy tape device driver # -# CONFIG_DRM is not set # CONFIG_RAW_DRIVER is not set # +# TPM devices +# + +# # I2C support # # CONFIG_I2C is not set +# CONFIG_I2C_SENSOR is not set # # Dallas's 1-wire bus @@ -432,6 +478,11 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_W1 is not set # +# Hardware Monitoring support +# +# CONFIG_HWMON is not set + +# # Misc devices # @@ -453,9 +504,9 @@ CONFIG_LEGACY_PTY_COUNT=256 # # Console display driver support # -# CONFIG_VGA_CONSOLE is not set +CONFIG_VGA_CONSOLE=y +# CONFIG_MDA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -469,10 +520,6 @@ CONFIG_DUMMY_CONSOLE=y # CONFIG_USB_ARCH_HAS_OHCI is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# - -# # USB Gadget Support # # CONFIG_USB_GADGET is not set @@ -488,19 +535,28 @@ CONFIG_DUMMY_CONSOLE=y # CONFIG_INFINIBAND is not set # +# SN Devices +# + +# # File systems # -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y # CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y +# CONFIG_DNOTIFY is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set @@ -520,12 +576,8 @@ CONFIG_DNOTIFY=y # # Pseudo filesystems # -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS_XATTR=y -CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_PROC_FS is not set +# CONFIG_SYSFS is not set # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y @@ -533,13 +585,7 @@ CONFIG_RAMFS=y # # Miscellaneous filesystems # -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set # CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set # CONFIG_CRAMFS is not set # CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set @@ -551,23 +597,18 @@ CONFIG_RAMFS=y # Network File Systems # CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -CONFIG_NFSD=y -# CONFIG_NFSD_V3 is not set -# CONFIG_NFSD_TCP is not set +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y -CONFIG_EXPORTFS=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set # # Partition Types @@ -581,22 +622,18 @@ CONFIG_MSDOS_PARTITION=y # CONFIG_NLS is not set # -# Profiling support -# -# CONFIG_PROFILING is not set - -# # Kernel hacking # +# CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="ip=bootp ether=46,0x03fe0300,eth0" +CONFIG_CMDLINE="console=ttyS0 debug ip=172.20.0.2:172.20.0.1::255.255.0.0" # # Security options # -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y +# CONFIG_KEYS is not set # CONFIG_SECURITY is not set # @@ -612,7 +649,7 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y # Library routines # # CONFIG_CRC_CCITT is not set -# CONFIG_CRC32 is not set -CONFIG_LIBCRC32C=m +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig index d0c85a4009d6..17d4fce6c4c6 100644 --- a/arch/mips/configs/rm200_defconfig +++ b/arch/mips/configs/rm200_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:09 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -91,6 +91,7 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_ARC=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_GENERIC_ISA_DMA=y CONFIG_I8259=y CONFIG_CPU_LITTLE_ENDIAN=y diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig index 84978b70714b..1dc935f37582 100644 --- a/arch/mips/configs/sb1250-swarm_defconfig +++ b/arch/mips/configs/sb1250-swarm_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:10 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig index 7c718a429b04..dd07e866b128 100644 --- a/arch/mips/configs/sead_defconfig +++ b/arch/mips/configs/sead_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:10 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -80,6 +80,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_BOARDS_GEN=y diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig index e01727cd0fe9..c9d3f83caf0f 100644 --- a/arch/mips/configs/tb0226_defconfig +++ b/arch/mips/configs/tb0226_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:12 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -95,6 +95,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 diff --git a/arch/mips/configs/tb0229_defconfig b/arch/mips/configs/tb0229_defconfig index c6ba3de27614..2cb669188aa9 100644 --- a/arch/mips/configs/tb0229_defconfig +++ b/arch/mips/configs/tb0229_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:12 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -98,6 +98,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig index 915c43b6e2d9..16e07fca446f 100644 --- a/arch/mips/configs/workpad_defconfig +++ b/arch/mips/configs/workpad_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:12 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -96,6 +96,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig index 562f2b8043ac..6d2290777ad7 100644 --- a/arch/mips/configs/yosemite_defconfig +++ b/arch/mips/configs/yosemite_defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:49:13 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c index 5f027bfa4af8..9ffe1a9142ca 100644 --- a/arch/mips/ddb5xxx/ddb5477/irq.c +++ b/arch/mips/ddb5xxx/ddb5477/irq.c @@ -76,7 +76,7 @@ set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger) extern void vrc5477_irq_init(u32 base); extern void mips_cpu_irq_init(u32 base); extern asmlinkage void ddb5477_handle_int(void); -extern int setup_irq(unsigned int irq, struct irqaction *irqaction); +extern int setup_irq(unsigned int irq, struct irqaction *irqaction); static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL }; void __init arch_init_irq(void) @@ -94,7 +94,7 @@ void __init arch_init_irq(void) /* setup PCI interrupt attributes */ set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE); set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE); - if (mips_machtype == MACH_NEC_ROCKHOPPERII) + if (mips_machtype == MACH_NEC_ROCKHOPPERII) set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE); else set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE); @@ -134,7 +134,7 @@ void __init arch_init_irq(void) /* setup cascade interrupts */ setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade); - setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade); + setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade); /* hook up the first-level interrupt handler */ set_except_vector(0, ddb5477_handle_int); diff --git a/arch/mips/ddb5xxx/ddb5477/setup.c b/arch/mips/ddb5xxx/ddb5477/setup.c index 15c6e543b56f..d62f5a789b05 100644 --- a/arch/mips/ddb5xxx/ddb5477/setup.c +++ b/arch/mips/ddb5xxx/ddb5477/setup.c @@ -141,7 +141,7 @@ static void __init ddb_time_init(void) /* mips_hpt_frequency is 1/2 of the cpu core freq */ i = (read_c0_config() >> 28 ) & 7; - if ((current_cpu_data.cputype == CPU_R5432) && (i == 3)) + if ((current_cpu_data.cputype == CPU_R5432) && (i == 3)) i = 4; mips_hpt_frequency = bus_frequency*(i+4)/4; } @@ -298,11 +298,11 @@ static void __init ddb5477_board_init(void) if (mips_machtype == MACH_NEC_ROCKHOPPER || mips_machtype == MACH_NEC_ROCKHOPPERII) { - /* Disable bus diagnostics. */ + /* Disable bus diagnostics. */ ddb_out32(DDB_PCICTL0_L, 0); ddb_out32(DDB_PCICTL0_H, 0); ddb_out32(DDB_PCICTL1_L, 0); - ddb_out32(DDB_PCICTL1_H, 0); + ddb_out32(DDB_PCICTL1_H, 0); } if (mips_machtype == MACH_NEC_ROCKHOPPER) { @@ -354,7 +354,7 @@ static void __init ddb5477_board_init(void) */ pci_write_config_byte(&dev_m1533, 0x58, 0x74); - /* + /* * positive decode (bit6 -0) * enable IDE controler interrupt (bit 4 -1) * setup SIRQ to point to IRQ 14 (bit 3:0 - 1101) @@ -364,31 +364,31 @@ static void __init ddb5477_board_init(void) /* Setup M5229 registers */ dev_m5229.bus = &bus; dev_m5229.sysdata = NULL; - dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE + dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE /* * enable IDE in the M5229 config register 0x50 (bit 0 - 1) - * M5229 IDSEL is addr:15; see above setting + * M5229 IDSEL is addr:15; see above setting */ pci_read_config_byte(&dev_m5229, 0x50, &temp8); pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1); - /* - * enable bus master (bit 2) and IO decoding (bit 0) + /* + * enable bus master (bit 2) and IO decoding (bit 0) */ pci_read_config_byte(&dev_m5229, 0x04, &temp8); pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5); /* * enable native, copied from arch/ppc/k2boot/head.S - * TODO - need volatile, need to be portable + * TODO - need volatile, need to be portable */ pci_write_config_byte(&dev_m5229, 0x09, 0xef); - /* Set Primary Channel Command Block Timing */ + /* Set Primary Channel Command Block Timing */ pci_write_config_byte(&dev_m5229, 0x59, 0x31); - /* + /* * Enable primary channel 40-pin cable * M5229 register 0x4a (bit 0) */ diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c index 133fb7c48e6c..6dbce92eb068 100644 --- a/arch/mips/dec/ecc-berr.c +++ b/arch/mips/dec/ecc-berr.c @@ -253,7 +253,7 @@ static inline void dec_kn03_be_init(void) kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR); kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN); - + /* * Set normal ECC detection and generation, enable ECC correction. * For KN05 we also need to make sure EE (?) is enabled in the MB. diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S index 3b3790993219..c89768d5c4e5 100644 --- a/arch/mips/dec/int-handler.S +++ b/arch/mips/dec/int-handler.S @@ -133,7 +133,7 @@ */ mfc0 t0,CP0_CAUSE # get pending interrupts mfc0 t1,CP0_STATUS -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT lw t2,cpu_fpu_mask #endif andi t0,ST0_IM # CAUSE.CE may be non-zero! @@ -141,7 +141,7 @@ beqz t0,spurious -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT and t2,t0 bnez t2,fpu # handle FPU immediately #endif @@ -271,7 +271,7 @@ handle_it: j ret_from_irq nop -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT fpu: j handle_fpe_int nop diff --git a/arch/mips/dec/prom/Makefile b/arch/mips/dec/prom/Makefile index 373822ec2d8c..bcd0247b3a66 100644 --- a/arch/mips/dec/prom/Makefile +++ b/arch/mips/dec/prom/Makefile @@ -5,7 +5,7 @@ lib-y += init.o memory.o cmdline.o identify.o console.o -lib-$(CONFIG_MIPS32) += locore.o -lib-$(CONFIG_MIPS64) += call_o32.o +lib-$(CONFIG_32BIT) += locore.o +lib-$(CONFIG_64BIT) += call_o32.o EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/defconfig b/arch/mips/defconfig index d55fe665926f..20f84b119b4c 100644 --- a/arch/mips/defconfig +++ b/arch/mips/defconfig @@ -4,9 +4,9 @@ # Wed Jan 26 02:48:59 2005 # CONFIG_MIPS=y -# CONFIG_MIPS64 is not set # CONFIG_64BIT is not set -CONFIG_MIPS32=y +# CONFIG_64BIT is not set +CONFIG_32BIT=y # # Code maturity level options @@ -90,6 +90,7 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_HAVE_DEC_LOCK=y CONFIG_ARC=y CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_IRQ_CPU=y CONFIG_SWAP_IO_SPACE=y diff --git a/arch/mips/ite-boards/generic/it8172_setup.c b/arch/mips/ite-boards/generic/it8172_setup.c index d808a67294b8..a5f6d84bc181 100644 --- a/arch/mips/ite-boards/generic/it8172_setup.c +++ b/arch/mips/ite-boards/generic/it8172_setup.c @@ -129,7 +129,7 @@ static void __init it8172_setup(void) /* * IO/MEM resources. - * + * * revisit this area. */ set_io_port_base(KSEG1); diff --git a/arch/mips/ite-boards/generic/time.c b/arch/mips/ite-boards/generic/time.c index 30a6c0d5fc50..f5d67ee21ac6 100644 --- a/arch/mips/ite-boards/generic/time.c +++ b/arch/mips/ite-boards/generic/time.c @@ -72,7 +72,7 @@ static inline int rtc_dm_binary(void) { return saved_control & RTC_DM_BINARY; } static inline unsigned char bin_to_hw(unsigned char c) { - if (rtc_dm_binary()) + if (rtc_dm_binary()) return c; else return ((c/10) << 4) + (c%10); @@ -91,9 +91,9 @@ hw_to_bin(unsigned char c) static inline unsigned char hour_bin_to_hw(unsigned char c) { - if (rtc_24h()) + if (rtc_24h()) return bin_to_hw(c); - if (c >= 12) + if (c >= 12) return 0x80 | bin_to_hw((c==12)?12:c-12); /* 12 is 12pm */ else return bin_to_hw((c==0)?12:c); /* 0 is 12 AM, not 0 am */ @@ -105,9 +105,9 @@ hour_hw_to_bin(unsigned char c) unsigned char tmp = hw_to_bin(c&0x3f); if (rtc_24h()) return tmp; - if (c & 0x80) + if (c & 0x80) return (tmp==12)?12:tmp+12; /* 12pm is 12, not 24 */ - else + else return (tmp==12)?0:tmp; /* 12am is 0 */ } @@ -145,7 +145,7 @@ static unsigned long __init cal_r4koff(void) return (mips_hpt_frequency / HZ); } -static unsigned long +static unsigned long it8172_rtc_get_time(void) { unsigned int year, mon, day, hour, min, sec; @@ -166,12 +166,12 @@ it8172_rtc_get_time(void) hour = hour_hw_to_bin(CMOS_READ(RTC_HOURS)); day = hw_to_bin(CMOS_READ(RTC_DAY_OF_MONTH)); mon = hw_to_bin(CMOS_READ(RTC_MONTH)); - year = hw_to_bin(CMOS_READ(RTC_YEAR)) + + year = hw_to_bin(CMOS_READ(RTC_YEAR)) + hw_to_bin(*rtc_century_reg) * 100; /* restore interrupts */ local_irq_restore(flags); - + return mktime(year, mon, day, hour, min, sec); } diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index a0230ee0f7f4..d3303584fbd1 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -13,8 +13,8 @@ binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \ ifdef CONFIG_MODULES obj-y += mips_ksyms.o module.o -obj-$(CONFIG_MIPS32) += module-elf32.o -obj-$(CONFIG_MIPS64) += module-elf64.o +obj-$(CONFIG_32BIT) += module-elf32.o +obj-$(CONFIG_64BIT) += module-elf64.o endif obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o @@ -45,8 +45,8 @@ obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o obj-$(CONFIG_IRQ_MV64340) += irq-mv6434x.o -obj-$(CONFIG_MIPS32) += scall32-o32.o -obj-$(CONFIG_MIPS64) += scall64-64.o +obj-$(CONFIG_32BIT) += scall32-o32.o +obj-$(CONFIG_64BIT) += scall64-64.o obj-$(CONFIG_BINFMT_IRIX) += binfmt_irix.o obj-$(CONFIG_MIPS32_COMPAT) += ioctl32.o linux32.o signal32.o obj-$(CONFIG_MIPS32_N32) += binfmt_elfn32.o scall64-n32.o signal_n32.o @@ -55,7 +55,7 @@ obj-$(CONFIG_MIPS32_O32) += binfmt_elfo32.o scall64-o32.o ptrace32.o obj-$(CONFIG_KGDB) += gdb-low.o gdb-stub.o obj-$(CONFIG_PROC_FS) += proc.o -obj-$(CONFIG_MIPS64) += cpu-bugs64.o +obj-$(CONFIG_64BIT) += cpu-bugs64.o obj-$(CONFIG_GEN_RTC) += genrtc.o diff --git a/arch/mips/kernel/binfmt_elfn32.c b/arch/mips/kernel/binfmt_elfn32.c index ed47041f3030..6b645fbb1ddc 100644 --- a/arch/mips/kernel/binfmt_elfn32.c +++ b/arch/mips/kernel/binfmt_elfn32.c @@ -103,7 +103,7 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value) * Convert jiffies to nanoseconds and seperate with * one divide. */ - u64 nsec = (u64)jiffies * TICK_NSEC; + u64 nsec = (u64)jiffies * TICK_NSEC; value->tv_sec = div_long_long_rem(nsec, NSEC_PER_SEC, &value->tv_usec); value->tv_usec /= NSEC_PER_USEC; } diff --git a/arch/mips/kernel/binfmt_elfo32.c b/arch/mips/kernel/binfmt_elfo32.c index ee21b18c37a8..b4075e99c452 100644 --- a/arch/mips/kernel/binfmt_elfo32.c +++ b/arch/mips/kernel/binfmt_elfo32.c @@ -105,7 +105,7 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value) * Convert jiffies to nanoseconds and seperate with * one divide. */ - u64 nsec = (u64)jiffies * TICK_NSEC; + u64 nsec = (u64)jiffies * TICK_NSEC; value->tv_sec = div_long_long_rem(nsec, NSEC_PER_SEC, &value->tv_usec); value->tv_usec /= NSEC_PER_USEC; } diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c index 11ebe5d4c446..47a087b6c11b 100644 --- a/arch/mips/kernel/cpu-bugs64.c +++ b/arch/mips/kernel/cpu-bugs64.c @@ -137,7 +137,7 @@ static inline void check_mult_sh(void) for (i = 0; i < 8; i++) if (v1[i] != w[i]) bug = 1; - + if (bug == 0) { printk("no.\n"); return; @@ -149,7 +149,7 @@ static inline void check_mult_sh(void) for (i = 0; i < 8; i++) if (v2[i] != w[i]) fix = 0; - + if (fix == 1) { printk("yes.\n"); return; diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 4bb849582314..7685f8baf3f0 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -229,15 +229,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_VR41XX: switch (c->processor_id & 0xf0) { -#ifndef CONFIG_VR4181 case PRID_REV_VR4111: c->cputype = CPU_VR4111; break; -#else - case PRID_REV_VR4181: - c->cputype = CPU_VR4181; - break; -#endif case PRID_REV_VR4121: c->cputype = CPU_VR4121; break; diff --git a/arch/mips/kernel/gdb-low.S b/arch/mips/kernel/gdb-low.S index ece6ddaf7011..512bedbfa7b9 100644 --- a/arch/mips/kernel/gdb-low.S +++ b/arch/mips/kernel/gdb-low.S @@ -13,13 +13,13 @@ #include <asm/stackframe.h> #include <asm/gdb-stub.h> -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT #define DMFC0 mfc0 #define DMTC0 mtc0 #define LDC1 lwc1 #define SDC1 lwc1 #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define DMFC0 dmfc0 #define DMTC0 dmtc0 #define LDC1 ldc1 diff --git a/arch/mips/kernel/gdb-stub.c b/arch/mips/kernel/gdb-stub.c index 269889302a27..d3fd1ab14274 100644 --- a/arch/mips/kernel/gdb-stub.c +++ b/arch/mips/kernel/gdb-stub.c @@ -687,8 +687,8 @@ void handle_exception (struct gdb_regs *regs) * acquire the big kgdb spinlock */ if (!spin_trylock(&kgdb_lock)) { - /* - * some other CPU has the lock, we should go back to + /* + * some other CPU has the lock, we should go back to * receive the gdb_wait IPC */ return; @@ -703,7 +703,7 @@ void handle_exception (struct gdb_regs *regs) async_bp.addr = 0; } - /* + /* * acquire the CPU spinlocks */ for (i = num_online_cpus()-1; i >= 0; i--) @@ -894,7 +894,7 @@ void handle_exception (struct gdb_regs *regs) ptr = &input_buffer[1]; if (hexToLong(&ptr, &addr)) regs->cp0_epc = addr; - + goto exit_kgdb_exception; break; @@ -1001,7 +1001,7 @@ void breakpoint(void) return; __asm__ __volatile__( - ".globl breakinst\n\t" + ".globl breakinst\n\t" ".set\tnoreorder\n\t" "nop\n" "breakinst:\tbreak\n\t" @@ -1014,7 +1014,7 @@ void breakpoint(void) void async_breakpoint(void) { __asm__ __volatile__( - ".globl async_breakinst\n\t" + ".globl async_breakinst\n\t" ".set\tnoreorder\n\t" "nop\n" "async_breakinst:\tbreak\n\t" diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index a5b0a389b063..e7f6c1b90806 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -54,7 +54,7 @@ NESTED(except_vec3_generic, 0, sp) #endif mfc0 k1, CP0_CAUSE andi k1, k1, 0x7c -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT dsll k1, k1, 1 #endif PTR_L k0, exception_handlers(k1) @@ -81,7 +81,7 @@ NESTED(except_vec3_r4000, 0, sp) beq k1, k0, handle_vced li k0, 14<<2 beq k1, k0, handle_vcei -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT dsll k1, k1, 1 #endif .set pop @@ -244,12 +244,12 @@ NESTED(nmi_handler, PT_SIZE, sp) start with an n and gas will believe \n is ok ... */ .macro __BUILD_verbose nexception LONG_L a1, PT_EPC(sp) -#if CONFIG_MIPS32 +#ifdef CONFIG_32BIT PRINT("Got \nexception at %08lx\012") -#endif -#if CONFIG_MIPS64 +#endif +#ifdef CONFIG_64BIT PRINT("Got \nexception at %016lx\012") -#endif +#endif .endm .macro __BUILD_count exception @@ -293,7 +293,7 @@ NESTED(nmi_handler, PT_SIZE, sp) BUILD_HANDLER mcheck mcheck cli verbose /* #24 */ BUILD_HANDLER reserved reserved sti verbose /* others */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* A temporary overflow handler used by check_daddi(). */ __INIT diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index a64e87d22014..2a1b45d66f04 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -107,7 +107,7 @@ .endm .macro setup_c0_status_pri -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT setup_c0_status ST0_KX 0 #else setup_c0_status 0 0 @@ -115,7 +115,7 @@ .endm .macro setup_c0_status_sec -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT setup_c0_status ST0_KX ST0_BEV #else setup_c0_status 0 ST0_BEV @@ -215,7 +215,7 @@ NESTED(smp_bootstrap, 16, sp) * slightly different layout ... */ page swapper_pg_dir, _PGD_ORDER -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT page invalid_pmd_table, _PMD_ORDER #endif page invalid_pte_table, _PTE_ORDER diff --git a/arch/mips/kernel/ioctl32.c b/arch/mips/kernel/ioctl32.c index 519cd5d0aebb..c069719ff0d8 100644 --- a/arch/mips/kernel/ioctl32.c +++ b/arch/mips/kernel/ioctl32.c @@ -27,7 +27,7 @@ long sys_ioctl(unsigned int fd, unsigned int cmd, unsigned long arg); #include "compat_ioctl.c" typedef int (* ioctl32_handler_t)(unsigned int, unsigned int, unsigned long, struct file *); - + #define COMPATIBLE_IOCTL(cmd) HANDLE_IOCTL((cmd),sys_ioctl) #define HANDLE_IOCTL(cmd,handler) { (cmd), (ioctl32_handler_t)(handler), NULL }, #define IOCTL_TABLE_START \ diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 441157a1f994..7d93992e462c 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -77,7 +77,7 @@ int show_interrupts(struct seq_file *p, void *v) if (i < NR_IRQS) { spin_lock_irqsave(&irq_desc[i].lock, flags); action = irq_desc[i].action; - if (!action) + if (!action) goto skip; seq_printf(p, "%3d: ",i); #ifndef CONFIG_SMP diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c index 993abc868e54..ece4564919d8 100644 --- a/arch/mips/kernel/linux32.c +++ b/arch/mips/kernel/linux32.c @@ -313,7 +313,7 @@ asmlinkage int sys32_sysinfo(struct sysinfo32 *info) struct sysinfo s; int ret, err; mm_segment_t old_fs = get_fs (); - + set_fs (KERNEL_DS); ret = sys_sysinfo(&s); set_fs (old_fs); @@ -546,21 +546,21 @@ struct msgbuf32 { s32 mtype; char mtext[1]; }; struct ipc_perm32 { key_t key; - compat_uid_t uid; - compat_gid_t gid; - compat_uid_t cuid; - compat_gid_t cgid; + __compat_uid_t uid; + __compat_gid_t gid; + __compat_uid_t cuid; + __compat_gid_t cgid; compat_mode_t mode; unsigned short seq; }; struct ipc64_perm32 { key_t key; - compat_uid_t uid; - compat_gid_t gid; - compat_uid_t cuid; - compat_gid_t cgid; - compat_mode_t mode; + __compat_uid_t uid; + __compat_gid_t gid; + __compat_uid_t cuid; + __compat_gid_t cgid; + compat_mode_t mode; unsigned short seq; unsigned short __pad1; unsigned int __unused1; @@ -1334,17 +1334,17 @@ asmlinkage int sys32_sendfile(int out_fd, int in_fd, compat_off_t *offset, mm_segment_t old_fs = get_fs(); int ret; off_t of; - + if (offset && get_user(of, offset)) return -EFAULT; - + set_fs(KERNEL_DS); ret = sys_sendfile(out_fd, in_fd, offset ? &of : NULL, count); set_fs(old_fs); - + if (offset && put_user(of, offset)) return -EFAULT; - + return ret; } @@ -1362,11 +1362,11 @@ static unsigned char socketcall_nargs[18]={AL(0),AL(3),AL(3),AL(3),AL(2),AL(3), #undef AL /* - * System call vectors. + * System call vectors. * * Argument checking cleaned up. Saved 20% in size. * This function doesn't need to set the kernel lock because - * it is set by the callees. + * it is set by the callees. */ asmlinkage long sys32_socketcall(int call, unsigned int *args32) @@ -1402,11 +1402,11 @@ asmlinkage long sys32_socketcall(int call, unsigned int *args32) /* copy_from_user should be SMP safe. */ if (copy_from_user(a, args32, socketcall_nargs[call])) return -EFAULT; - + a0=a[0]; a1=a[1]; - - switch(call) + + switch(call) { case SYS_SOCKET: err = sys_socket(a0,a1,a[2]); diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c index eed29fc9dc82..86e42c633f73 100644 --- a/arch/mips/kernel/mips_ksyms.c +++ b/arch/mips/kernel/mips_ksyms.c @@ -35,7 +35,7 @@ EXPORT_SYMBOL(memcpy); EXPORT_SYMBOL(memmove); EXPORT_SYMBOL(strcat); EXPORT_SYMBOL(strchr); -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT EXPORT_SYMBOL(strncmp); #endif EXPORT_SYMBOL(strlen); diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 6e70c42c2058..e4f2f8011387 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -70,7 +70,7 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) /* New thread loses kernel privileges. */ status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|KU_MASK); -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT status &= ~ST0_FR; status |= (current->thread.mflags & MF_32BIT_REGS) ? 0 : ST0_FR; #endif @@ -236,10 +236,10 @@ static int __init get_frame_info(struct mips_frame_info *info, void *func) break; if ( -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT ip->i_format.opcode == sw_op && #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT ip->i_format.opcode == sd_op && #endif ip->i_format.rs == 29) @@ -353,7 +353,7 @@ schedule_timeout_caller: out: -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT if (current->thread.mflags & MF_32BIT_REGS) /* Kludge for 32-bit ps */ pc &= 0xffffffffUL; #endif diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 92e70ca3bff9..0b571a5b4b83 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -124,7 +124,7 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data) if (tsk_used_math(child)) { fpureg_t *fregs = get_fpu_regs(child); -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT /* * The odd registers are actually the high * order bits of the values stored in the even @@ -135,7 +135,7 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data) else tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff); #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT tmp = fregs[addr - FPR_BASE]; #endif } else { @@ -213,7 +213,7 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data) sizeof(child->thread.fpu.hard)); child->thread.fpu.hard.fcr31 = 0; } -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT /* * The odd registers are actually the high order bits * of the values stored in the even registers - unless @@ -227,7 +227,7 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data) fregs[addr - FPR_BASE] |= data; } #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT fregs[addr - FPR_BASE] = data; #endif break; @@ -304,14 +304,14 @@ out: static inline int audit_arch(void) { #ifdef CONFIG_CPU_LITTLE_ENDIAN -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT if (!(current->thread.mflags & MF_32BIT_REGS)) return AUDIT_ARCH_MIPSEL64; #endif /* MIPS64 */ return AUDIT_ARCH_MIPSEL; #else /* big endian... */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT if (!(current->thread.mflags & MF_32BIT_REGS)) return AUDIT_ARCH_MIPS64; #endif /* MIPS64 */ diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S index 243e7b629af6..f10019640ee9 100644 --- a/arch/mips/kernel/r2300_switch.S +++ b/arch/mips/kernel/r2300_switch.S @@ -35,7 +35,7 @@ /* * FPU context is saved iff the process has used it's FPU in the current * time slice as indicated by TIF_USEDFPU. In any case, the CU1 bit for user - * space STATUS register should be 0, so that a process *always* starts its + * space STATUS register should be 0, so that a process *always* starts its * userland with FPU disabled after each context switch. * * FPU will be enabled as soon as the process accesses FPU again, through @@ -55,7 +55,7 @@ LEAF(resume) cpu_save_nonscratch a0 sw ra, THREAD_REG31(a0) - /* + /* * check if we need to save FPU registers */ lw t3, TASK_THREAD_INFO(a0) diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S index ebb643d8d14c..aba665bcb386 100644 --- a/arch/mips/kernel/r4k_fpu.S +++ b/arch/mips/kernel/r4k_fpu.S @@ -36,7 +36,7 @@ LEAF(_save_fp_context) cfc1 t1, fcr31 -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* Store the 16 odd double precision registers */ EX sdc1 $f1, SC_FPREGS+8(a0) EX sdc1 $f3, SC_FPREGS+24(a0) @@ -118,7 +118,7 @@ LEAF(_save_fp_context32) */ LEAF(_restore_fp_context) EX lw t0, SC_FPC_CSR(a0) -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT EX ldc1 $f1, SC_FPREGS+8(a0) EX ldc1 $f3, SC_FPREGS+24(a0) EX ldc1 $f5, SC_FPREGS+40(a0) diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index 1fc3b2eb12bd..e02b7722ccb8 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S @@ -33,7 +33,7 @@ /* * FPU context is saved iff the process has used it's FPU in the current * time slice as indicated by _TIF_USEDFPU. In any case, the CU1 bit for user - * space STATUS register should be 0, so that a process *always* starts its + * space STATUS register should be 0, so that a process *always* starts its * userland with FPU disabled after each context switch. * * FPU will be enabled as soon as the process accesses FPU again, through @@ -105,7 +105,7 @@ * Save a thread's fp context. */ LEAF(_save_fp) -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT mfc0 t1, CP0_STATUS #endif fpu_save_double a0 t1 t0 t2 # clobbers t1 @@ -142,7 +142,7 @@ LEAF(_init_fpu) li t1, -1 # SNaN -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT sll t0, t0, 5 bgez t0, 1f # 16 / 32 register mode? @@ -164,7 +164,7 @@ LEAF(_init_fpu) dmtc1 t1, $f31 1: #endif - + #ifdef CONFIG_CPU_MIPS32 mtc1 t1, $f0 mtc1 t1, $f1 diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 3a240e3e004c..12b531c295c4 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -241,7 +241,7 @@ static inline int parse_rd_cmdline(unsigned long* rd_start, unsigned long* rd_en if (*tmp) strcat(command_line, tmp); -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* HACK: Guess if the sign extension was forgotten */ if (start > 0x0000000080000000 && start < 0x00000000ffffffff) start |= 0xffffffff00000000; @@ -446,7 +446,7 @@ static inline void resource_init(void) { int i; -#if defined(CONFIG_MIPS64) && !defined(CONFIG_BUILD_ELF64) +#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64) /* * The 64bit code in 32bit object format trick can't represent * 64bit wide relocations for linker script symbols. diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index f6875f023a29..8ddfbd8d425a 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -558,7 +558,7 @@ static inline int setup_sigcontext32(struct pt_regs *regs, if (!used_math()) goto out; - /* + /* * Save FPU state to signal context. Signal handler will "inherit" * current FPU state. */ diff --git a/arch/mips/kernel/sysirix.c b/arch/mips/kernel/sysirix.c index f3bf0e43b8bb..b46595462717 100644 --- a/arch/mips/kernel/sysirix.c +++ b/arch/mips/kernel/sysirix.c @@ -632,10 +632,7 @@ asmlinkage int irix_stime(int value) write_seqlock_irq(&xtime_lock); xtime.tv_sec = value; xtime.tv_nsec = 0; - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); write_sequnlock_irq(&xtime_lock); return 0; diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index 648c82292ed6..0dd0df7a3b04 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -223,10 +223,7 @@ int do_settimeofday(struct timespec *tv) set_normalized_timespec(&xtime, sec, nsec); set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; + ntp_clear(); write_sequnlock_irq(&xtime_lock); clock_was_set(); @@ -442,7 +439,7 @@ irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) * called as close as possible to 500 ms before the new second starts. */ write_seqlock(&xtime_lock); - if ((time_status & STA_UNSYNC) == 0 && + if (ntp_synced() && xtime.tv_sec > last_rtc_update + 660 && (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 && (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) { diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 56c36e42e0a6..a53b1ed7b386 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -924,7 +924,7 @@ void __init per_cpu_trap_init(void) * flag that some firmware may have left set and the TS bit (for * IP27). Set XX for ISA IV code to work. */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; #endif if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index 3f24a1d45865..36c5212e0928 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -240,7 +240,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, break; case lwu_op: -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * A 32-bit kernel might be running on a 64-bit processor. But * if we're on a 32-bit processor and an i-cache incoherency @@ -278,13 +278,13 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, *newvalue = value; *regptr = ®s->regs[insn.i_format.rt]; break; -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ /* Cannot handle 64-bit instructions in 32-bit kernel */ goto sigill; case ld_op: -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * A 32-bit kernel might be running on a 64-bit processor. But * if we're on a 32-bit processor and an i-cache incoherency @@ -320,7 +320,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, *newvalue = value; *regptr = ®s->regs[insn.i_format.rt]; break; -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ /* Cannot handle 64-bit instructions in 32-bit kernel */ goto sigill; @@ -392,7 +392,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, break; case sd_op: -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * A 32-bit kernel might be running on a 64-bit processor. But * if we're on a 32-bit processor and an i-cache incoherency @@ -428,7 +428,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, if (res) goto fault; break; -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ /* Cannot handle 64-bit instructions in 32-bit kernel */ goto sigill; diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index e830d788c106..482ac310c937 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -15,7 +15,7 @@ SECTIONS /* This is the value for an Origin kernel, taken from an IRIX kernel. */ /* . = 0xc00000000001c000; */ - /* Set the vaddr for the text segment to a value + /* Set the vaddr for the text segment to a value >= 0xa800 0000 0001 9000 if no symmon is going to configured >= 0xa800 0000 0030 0000 otherwise */ diff --git a/arch/mips/lasat/at93c.c b/arch/mips/lasat/at93c.c index f6add041ebec..ca26e554615e 100644 --- a/arch/mips/lasat/at93c.c +++ b/arch/mips/lasat/at93c.c @@ -1,7 +1,7 @@ -/* +/* * Atmel AT93C46 serial eeprom driver * - * Brian Murphy <brian.murphy@eicon.com> + * Brian Murphy <brian.murphy@eicon.com> * */ #include <linux/kernel.h> @@ -21,12 +21,12 @@ struct at93c_defs *at93c; -static void at93c_reg_write(u32 val) +static void at93c_reg_write(u32 val) { *at93c->reg = val; } -static u32 at93c_reg_read(void) +static u32 at93c_reg_read(void) { u32 tmp = *at93c->reg; return tmp; @@ -81,7 +81,7 @@ static u8 at93c_read_byte(void) } static void at93c_write_bits(u32 data, int size) -{ +{ int i; int shift = size - 1; u32 mask = (1 << shift); @@ -90,7 +90,7 @@ static void at93c_write_bits(u32 data, int size) at93c_write_databit((data & mask) >> shift); data <<= 1; } -} +} static void at93c_init_op(void) { @@ -104,8 +104,8 @@ static void at93c_end_op(void) lasat_ndelay(250); } -static void at93c_wait(void) -{ +static void at93c_wait(void) +{ at93c_init_op(); while (!at93c_read_databit()) ; diff --git a/arch/mips/lasat/at93c.h b/arch/mips/lasat/at93c.h index a912ac2171b0..cfe2f99b1d44 100644 --- a/arch/mips/lasat/at93c.h +++ b/arch/mips/lasat/at93c.h @@ -1,7 +1,7 @@ -/* +/* * Atmel AT93C46 serial eeprom driver * - * Brian Murphy <brian.murphy@eicon.com> + * Brian Murphy <brian.murphy@eicon.com> * */ diff --git a/arch/mips/lasat/ds1603.c b/arch/mips/lasat/ds1603.c index 7bbf6cf923c9..9d7812e03dcd 100644 --- a/arch/mips/lasat/ds1603.c +++ b/arch/mips/lasat/ds1603.c @@ -1,7 +1,7 @@ -/* - * Dallas Semiconductors 1603 RTC driver +/* + * Dallas Semiconductors 1603 RTC driver * - * Brian Murphy <brian@murphy.dk> + * Brian Murphy <brian@murphy.dk> * */ #include <linux/kernel.h> @@ -20,12 +20,12 @@ struct ds_defs *ds1603 = NULL; /* HW specific register functions */ -static void rtc_reg_write(unsigned long val) +static void rtc_reg_write(unsigned long val) { *ds1603->reg = val; } -static unsigned long rtc_reg_read(void) +static unsigned long rtc_reg_read(void) { unsigned long tmp = *ds1603->reg; return tmp; @@ -80,7 +80,7 @@ static unsigned int rtc_read_databit(void) { unsigned int data; - data = (rtc_datareg_read() & (1 << ds1603->data_read_shift)) + data = (rtc_datareg_read() & (1 << ds1603->data_read_shift)) >> ds1603->data_read_shift; rtc_cycle_clock(rtc_reg_read()); return data; diff --git a/arch/mips/lasat/ds1603.h b/arch/mips/lasat/ds1603.h index 55f3b0423c20..c2e5c76a379d 100644 --- a/arch/mips/lasat/ds1603.h +++ b/arch/mips/lasat/ds1603.h @@ -1,7 +1,7 @@ -/* - * Dallas Semiconductors 1603 RTC driver +/* + * Dallas Semiconductors 1603 RTC driver * - * Brian Murphy <brian@murphy.dk> + * Brian Murphy <brian@murphy.dk> * */ #ifndef __DS1603_H diff --git a/arch/mips/lasat/image/Makefile b/arch/mips/lasat/image/Makefile index 18b6430f11be..35ecd6483ef6 100644 --- a/arch/mips/lasat/image/Makefile +++ b/arch/mips/lasat/image/Makefile @@ -21,7 +21,7 @@ LDSCRIPT= -L$(obj) -Tromscript.normal HEAD_DEFINES := -D_kernel_start=0x$(KERNEL_START) \ -D_kernel_entry=0x$(KERNEL_ENTRY) \ -D VERSION="\"$(Version)\"" \ - -D TIMESTAMP=$(shell date +%s) + -D TIMESTAMP=$(shell date +%s) $(obj)/head.o: $(obj)/head.S $(KERNEL_IMAGE) $(CC) -fno-pic $(HEAD_DEFINES) -I$(TOPDIR)/include -c -o $@ $< diff --git a/arch/mips/lasat/image/head.S b/arch/mips/lasat/image/head.S index 426bd7de17bb..efb95f2609c2 100644 --- a/arch/mips/lasat/image/head.S +++ b/arch/mips/lasat/image/head.S @@ -27,5 +27,5 @@ reldate: .word TIMESTAMP .org 0x50 -release: +release: .string VERSION diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c index 1148a2d20aa7..c90da1639440 100644 --- a/arch/mips/lasat/interrupt.c +++ b/arch/mips/lasat/interrupt.c @@ -15,7 +15,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * - * Routines for generic manipulation of the interrupts found on the + * Routines for generic manipulation of the interrupts found on the * Lasat boards. */ #include <linux/init.h> @@ -101,7 +101,7 @@ static unsigned long get_int_status_100(void) return *lasat_int_status & *lasat_int_mask; } -static unsigned long get_int_status_200(void) +static unsigned long get_int_status_200(void) { unsigned long int_status; diff --git a/arch/mips/lasat/lasat_board.c b/arch/mips/lasat/lasat_board.c index 8c784bcf1111..fc9b0e2a6be1 100644 --- a/arch/mips/lasat/lasat_board.c +++ b/arch/mips/lasat/lasat_board.c @@ -67,7 +67,7 @@ static void init_flash_sizes(void) if (mips_machtype == MACH_LASAT_100) { lasat_board_info.li_flash_base = 0x1e000000; - + lb[LASAT_MTD_BOOTLOADER] = 0x1e400000; if (lasat_board_info.li_flash_size > 0x200000) { @@ -103,7 +103,7 @@ int lasat_init_board_info(void) memset(&lasat_board_info, 0, sizeof(lasat_board_info)); /* First read the EEPROM info */ - EEPROMRead(0, (unsigned char *)&lasat_board_info.li_eeprom_info, + EEPROMRead(0, (unsigned char *)&lasat_board_info.li_eeprom_info, sizeof(struct lasat_eeprom_struct)); /* Check the CRC */ @@ -188,7 +188,7 @@ int lasat_init_board_info(void) case 0x1: lasat_board_info.li_cpu_hz = lasat_board_info.li_bus_hz + - (lasat_board_info.li_bus_hz >> 1); + (lasat_board_info.li_bus_hz >> 1); break; case 0x2: lasat_board_info.li_cpu_hz = @@ -271,7 +271,7 @@ void lasat_write_eeprom_info(void) lasat_board_info.li_eeprom_info.crc32 = crc; /* Write the EEPROM info */ - EEPROMWrite(0, (unsigned char *)&lasat_board_info.li_eeprom_info, + EEPROMWrite(0, (unsigned char *)&lasat_board_info.li_eeprom_info, sizeof(struct lasat_eeprom_struct)); } diff --git a/arch/mips/lasat/picvue.c b/arch/mips/lasat/picvue.c index 5637cd153926..9ae82c3ffb07 100644 --- a/arch/mips/lasat/picvue.c +++ b/arch/mips/lasat/picvue.c @@ -1,7 +1,7 @@ -/* +/* * Picvue PVC160206 display driver * - * Brian Murphy <brian@murphy.dk> + * Brian Murphy <brian@murphy.dk> * */ #include <linux/kernel.h> @@ -24,12 +24,12 @@ struct pvc_defs *picvue = NULL; DECLARE_MUTEX(pvc_sem); -static void pvc_reg_write(u32 val) +static void pvc_reg_write(u32 val) { *picvue->reg = val; } -static u32 pvc_reg_read(void) +static u32 pvc_reg_read(void) { u32 tmp = *picvue->reg; return tmp; @@ -65,12 +65,12 @@ static u8 pvc_read_data(void) { u32 data = pvc_reg_read(); u8 byte; - data |= picvue->rw; + data |= picvue->rw; data &= ~picvue->rs; pvc_reg_write(data); ndelay(40); byte = pvc_read_byte(data); - data |= picvue->rs; + data |= picvue->rs; pvc_reg_write(data); return byte; } diff --git a/arch/mips/lasat/picvue.h b/arch/mips/lasat/picvue.h index 74a39039135d..2a96bf971897 100644 --- a/arch/mips/lasat/picvue.h +++ b/arch/mips/lasat/picvue.h @@ -1,7 +1,7 @@ -/* +/* * Picvue PVC160206 display driver * - * Brian Murphy <brian.murphy@eicon.com> + * Brian Murphy <brian.murphy@eicon.com> * */ #include <asm/semaphore.h> diff --git a/arch/mips/lasat/picvue_proc.c b/arch/mips/lasat/picvue_proc.c index eaa2b4625124..cce7cddcdb08 100644 --- a/arch/mips/lasat/picvue_proc.c +++ b/arch/mips/lasat/picvue_proc.c @@ -1,7 +1,7 @@ -/* +/* * Picvue PVC160206 display driver * - * Brian Murphy <brian.murphy@eicon.com> + * Brian Murphy <brian.murphy@eicon.com> * */ #include <linux/kernel.h> @@ -51,10 +51,10 @@ static int pvc_proc_read_line(char *page, char **start, page += sprintf(page, "%s\n", pvc_lines[lineno]); up(&pvc_sem); - return page - origpage; + return page - origpage; } -static int pvc_proc_write_line(struct file *file, const char *buffer, +static int pvc_proc_write_line(struct file *file, const char *buffer, unsigned long count, void *data) { int origcount = count; @@ -119,7 +119,7 @@ static int pvc_proc_read_scroll(char *page, char **start, page += sprintf(page, "%d\n", scroll_dir * scroll_interval); up(&pvc_sem); - return page - origpage; + return page - origpage; } diff --git a/arch/mips/lasat/prom.c b/arch/mips/lasat/prom.c index ca62881c9e52..88c7ab871ec4 100644 --- a/arch/mips/lasat/prom.c +++ b/arch/mips/lasat/prom.c @@ -42,7 +42,7 @@ static void null_prom_putc(char c) /* these are functions provided by the bootloader */ static void (* prom_putc)(char c) = null_prom_putc; void (* prom_printf)(const char * fmt, ...) = null_prom_printf; -void (* prom_display)(const char *string, int pos, int clear) = +void (* prom_display)(const char *string, int pos, int clear) = null_prom_display; void (* prom_monitor)(void) = null_prom_monitor; diff --git a/arch/mips/lasat/reset.c b/arch/mips/lasat/reset.c index 37e4912ee1c8..8d7d7a454f9a 100644 --- a/arch/mips/lasat/reset.c +++ b/arch/mips/lasat/reset.c @@ -1,4 +1,4 @@ -/* +/* * Thomas Horsten <thh@lasat.com> * Copyright (C) 2000 LASAT Networks A/S. * diff --git a/arch/mips/lasat/setup.c b/arch/mips/lasat/setup.c index e371ed5cbe34..f2604fab9a99 100644 --- a/arch/mips/lasat/setup.c +++ b/arch/mips/lasat/setup.c @@ -105,7 +105,7 @@ static int lasat_panic_prom_monitor(struct notifier_block *this, return NOTIFY_DONE; } -static struct notifier_block lasat_panic_block[] = +static struct notifier_block lasat_panic_block[] = { { lasat_panic_display, NULL, INT_MAX }, { lasat_panic_prom_monitor, NULL, INT_MIN } @@ -120,7 +120,7 @@ static void lasat_timer_setup(struct irqaction *irq) { write_c0_compare( - read_c0_count() + + read_c0_count() + mips_hpt_frequency / HZ); change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5); } diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c index 1c0cc620a43f..8ff43a1c1e99 100644 --- a/arch/mips/lasat/sysctl.c +++ b/arch/mips/lasat/sysctl.c @@ -37,14 +37,14 @@ static DECLARE_MUTEX(lasat_info_sem); -/* Strategy function to write EEPROM after changing string entry */ +/* Strategy function to write EEPROM after changing string entry */ int sysctl_lasatstring(ctl_table *table, int *name, int nlen, void *oldval, size_t *oldlenp, void *newval, size_t newlen, void **context) { int r; down(&lasat_info_sem); - r = sysctl_string(table, name, + r = sysctl_string(table, name, nlen, oldval, oldlenp, newval, newlen, context); if (r < 0) { up(&lasat_info_sem); @@ -74,7 +74,7 @@ int proc_dolasatstring(ctl_table *table, int write, struct file *filp, return 0; } -/* proc function to write EEPROM after changing int entry */ +/* proc function to write EEPROM after changing int entry */ int proc_dolasatint(ctl_table *table, int write, struct file *filp, void *buffer, size_t *lenp, loff_t *ppos) { @@ -93,7 +93,7 @@ int proc_dolasatint(ctl_table *table, int write, struct file *filp, static int rtctmp; #ifdef CONFIG_DS1603 -/* proc function to read/write RealTime Clock */ +/* proc function to read/write RealTime Clock */ int proc_dolasatrtc(ctl_table *table, int write, struct file *filp, void *buffer, size_t *lenp, loff_t *ppos) { @@ -165,9 +165,9 @@ static char lasat_bcastaddr[16]; void update_bcastaddr(void) { unsigned int ip; - - ip = (lasat_board_info.li_eeprom_info.ipaddr & - lasat_board_info.li_eeprom_info.netmask) | + + ip = (lasat_board_info.li_eeprom_info.ipaddr & + lasat_board_info.li_eeprom_info.netmask) | ~lasat_board_info.li_eeprom_info.netmask; sprintf(lasat_bcastaddr, "%d.%d.%d.%d", @@ -205,7 +205,7 @@ int proc_lasat_ip(ctl_table *table, int write, struct file *filp, break; len++; } - if (len >= sizeof(proc_lasat_ipbuf)-1) + if (len >= sizeof(proc_lasat_ipbuf)-1) len = sizeof(proc_lasat_ipbuf) - 1; if (copy_from_user(proc_lasat_ipbuf, buffer, len)) { @@ -249,8 +249,8 @@ int proc_lasat_ip(ctl_table *table, int write, struct file *filp, } #endif /* defined(CONFIG_INET) */ -static int sysctl_lasat_eeprom_value(ctl_table *table, int *name, int nlen, - void *oldval, size_t *oldlenp, +static int sysctl_lasat_eeprom_value(ctl_table *table, int *name, int nlen, + void *oldval, size_t *oldlenp, void *newval, size_t newlen, void **context) { @@ -293,7 +293,7 @@ int proc_lasat_eeprom_value(ctl_table *table, int write, struct file *filp, if (!strcmp(filp->f_dentry->d_name.name, "debugaccess")) lasat_board_info.li_eeprom_info.debugaccess = lasat_board_info.li_debugaccess; } - lasat_write_eeprom_info(); + lasat_write_eeprom_info(); up(&lasat_info_sem); return 0; } @@ -316,8 +316,8 @@ static ctl_table lasat_table[] = { 0644, NULL, &proc_lasat_ip, &sysctl_lasat_intvec}, {LASAT_NETMASK, "netmask", &lasat_board_info.li_eeprom_info.netmask, sizeof(int), 0644, NULL, &proc_lasat_ip, &sysctl_lasat_intvec}, - {LASAT_BCAST, "bcastaddr", &lasat_bcastaddr, - sizeof(lasat_bcastaddr), 0600, NULL, + {LASAT_BCAST, "bcastaddr", &lasat_bcastaddr, + sizeof(lasat_bcastaddr), 0600, NULL, &proc_dostring, &sysctl_string}, #endif {LASAT_PASSWORD, "passwd_hash", &lasat_board_info.li_eeprom_info.passwd_hash, sizeof(lasat_board_info.li_eeprom_info.passwd_hash), diff --git a/arch/mips/lib-32/Makefile b/arch/mips/lib-32/Makefile index fd6a2bafdfcf..ad285786e74b 100644 --- a/arch/mips/lib-32/Makefile +++ b/arch/mips/lib-32/Makefile @@ -2,7 +2,7 @@ # Makefile for MIPS-specific library files.. # -lib-y += csum_partial.o memset.o watch.o +lib-y += csum_partial.o memset.o watch.o obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o diff --git a/arch/mips/lib-64/Makefile b/arch/mips/lib-64/Makefile index fd6a2bafdfcf..ad285786e74b 100644 --- a/arch/mips/lib-64/Makefile +++ b/arch/mips/lib-64/Makefile @@ -2,7 +2,7 @@ # Makefile for MIPS-specific library files.. # -lib-y += csum_partial.o memset.o watch.o +lib-y += csum_partial.o memset.o watch.o obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S index afa8eae18ff6..90ee8d43261f 100644 --- a/arch/mips/lib/memcpy.S +++ b/arch/mips/lib/memcpy.S @@ -79,7 +79,7 @@ /* * Only on the 64-bit kernel we can made use of 64-bit registers. */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define USE_DOUBLE #endif @@ -101,7 +101,7 @@ #define NBYTES 8 #define LOG_NBYTES 3 -/* +/* * As we are sharing code base with the mips32 tree (which use the o32 ABI * register definitions). We need to redefine the register definitions from * the n64 ABI register naming to the o32 ABI register naming. @@ -118,7 +118,7 @@ #define t5 $13 #define t6 $14 #define t7 $15 - + #else #define LOAD lw diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 20a552be02ee..99c550632d44 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -320,7 +320,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) case cop1_op: switch (MIPSInst_RS(ir)) { -#if __mips64 && !defined(SINGLE_ONLY_FPU) +#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) case dmfc_op: /* copregister fs -> gpr[rt] */ if (MIPSInst_RT(ir) != 0) { @@ -805,7 +805,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, ieee754dp d; ieee754sp s; int w; -#if __mips64 +#ifdef __mips64 s64 l; #endif } rv; /* resulting value */ @@ -950,7 +950,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, } #endif /* __mips >= 2 */ -#if __mips64 && !defined(SINGLE_ONLY_FPU) +#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) case fcvtl_op:{ ieee754sp fs; @@ -1125,7 +1125,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, } #endif -#if __mips64 && !defined(SINGLE_ONLY_FPU) +#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) case fcvtl_op:{ ieee754dp fs; @@ -1203,7 +1203,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, break; } -#if __mips64 && !defined(SINGLE_ONLY_FPU) +#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) case l_fmt:{ switch (MIPSInst_FUNC(ir)) { case fcvts_op: @@ -1267,7 +1267,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, case w_fmt: SITOREG(rv.w, MIPSInst_FD(ir)); break; -#if __mips64 && !defined(SINGLE_ONLY_FPU) +#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) case l_fmt: DITOREG(rv.l, MIPSInst_FD(ir)); break; diff --git a/arch/mips/math-emu/kernel_linkage.c b/arch/mips/math-emu/kernel_linkage.c index 04397fec30fc..4002f0cf79f3 100644 --- a/arch/mips/math-emu/kernel_linkage.c +++ b/arch/mips/math-emu/kernel_linkage.c @@ -86,7 +86,7 @@ int fpu_emulator_restore_context(struct sigcontext *sc) return err; } -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * This is the o32 version */ diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c index 8f1d875217a2..19d4b0792460 100644 --- a/arch/mips/mips-boards/atlas/atlas_int.c +++ b/arch/mips/mips-boards/atlas/atlas_int.c @@ -122,7 +122,7 @@ void __init arch_init_irq(void) int i; atlas_hw0_icregs = (struct atlas_ictrl_regs *)ioremap (ATLAS_ICTRL_REGS_BASE, sizeof(struct atlas_ictrl_regs *)); - + /* * Mask out all interrupt by writing "1" to all bit position in * the interrupt reset reg. diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c index 31caf0603a3f..311155d1d3ed 100644 --- a/arch/mips/mips-boards/generic/init.c +++ b/arch/mips/mips-boards/generic/init.c @@ -200,7 +200,7 @@ void __init kgdb_config (void) generic_putDebugChar = saa9730_putDebugChar; generic_getDebugChar = saa9730_getDebugChar; } - else + else #endif { speed = rs_kgdb_hook(line, speed); @@ -243,7 +243,7 @@ void __init prom_init(void) mips_revision_corid = MIPS_REVISION_CORID; if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { - if (BONITO_PCIDID == 0x0001df53 || + if (BONITO_PCIDID == 0x0001df53 || BONITO_PCIDID == 0x0003df53) mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; else @@ -310,7 +310,7 @@ void __init prom_init(void) case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_EMUL_MSC: - _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); + _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); #ifdef CONFIG_CPU_LITTLE_ENDIAN MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index fe7fc17305a6..16315444dd5a 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -89,7 +89,7 @@ static unsigned int __init estimate_cpu_frequency(void) * really calculate the timer frequency * For now we hardwire the SEAD board frequency to 12MHz. */ - + if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) || (prid == (PRID_COMP_MIPS | PRID_IMP_25KF))) count = 12000000; diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c index 3377e66de9eb..df6db6419ae9 100644 --- a/arch/mips/mips-boards/malta/malta_setup.c +++ b/arch/mips/mips-boards/malta/malta_setup.c @@ -149,15 +149,15 @@ static int __init malta_setup(void) argptr = prom_getcmdline(); if (strstr(argptr, "iobcuncached")) { BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; - BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & + BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); printk("Disabled Bonito IOBC coherency\n"); } else { BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; - BONITO_PCIMEMBASECFG |= - (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG |= + (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); printk("Disabled Bonito IOBC coherency\n"); } diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index f61e038b4440..b56a0abdc3d4 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -5,8 +5,8 @@ obj-y += cache.o extable.o fault.o init.o pgtable.o \ tlbex.o tlbex-fault.o -obj-$(CONFIG_MIPS32) += ioremap.o pgtable-32.o -obj-$(CONFIG_MIPS64) += pgtable-64.o +obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o +obj-$(CONFIG_64BIT) += pgtable-64.o obj-$(CONFIG_HIGHMEM) += highmem.o obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index a03ebb2cba67..5ea84bc98c6a 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -126,13 +126,13 @@ static inline void tx49_blast_icache32(void) CACHE32_UNROLL32_ALIGN2; /* I'm in even chunk. blast odd chunks */ - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start + 0x400; addr < end; addr += 0x400 * 2) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start + 0x400; addr < end; addr += 0x400 * 2) cache32_unroll32(addr|ws,Index_Invalidate_I); CACHE32_UNROLL32_ALIGN; /* I'm in odd chunk. blast even chunks */ - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400 * 2) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x400 * 2) cache32_unroll32(addr|ws,Index_Invalidate_I); } @@ -156,13 +156,13 @@ static inline void tx49_blast_icache32_page_indexed(unsigned long page) CACHE32_UNROLL32_ALIGN2; /* I'm in even chunk. blast odd chunks */ - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start + 0x400; addr < end; addr += 0x400 * 2) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start + 0x400; addr < end; addr += 0x400 * 2) cache32_unroll32(addr|ws,Index_Invalidate_I); CACHE32_UNROLL32_ALIGN; /* I'm in odd chunk. blast even chunks */ - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400 * 2) + for (ws = 0; ws < ws_end; ws += ws_inc) + for (addr = start; addr < end; addr += 0x400 * 2) cache32_unroll32(addr|ws,Index_Invalidate_I); } @@ -723,10 +723,10 @@ static void local_r4k_flush_cache_sigtramp(void * arg) ".set push\n\t" ".set noat\n\t" ".set mips3\n\t" -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT "la $at,1f\n\t" #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT "dla $at,1f\n\t" #endif "cache %0,($at)\n\t" diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c index ab30afd63b32..502f68c664b2 100644 --- a/arch/mips/mm/c-sb1.c +++ b/arch/mips/mm/c-sb1.c @@ -270,7 +270,7 @@ static void local_sb1_flush_icache_range(unsigned long start, __sb1_writeback_inv_dcache_all(); else __sb1_writeback_inv_dcache_range(start, end); - + /* Just flush the whole icache if the range is big enough */ if ((end - start) > icache_range_cutoff) __sb1_flush_icache_all(); diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c index 13d96d62764e..7166ffe63502 100644 --- a/arch/mips/mm/cerr-sb1.c +++ b/arch/mips/mm/cerr-sb1.c @@ -25,7 +25,7 @@ #include <asm/sibyte/sb1250_regs.h> #include <asm/sibyte/sb1250_scd.h> #endif - + /* SB1 definitions */ /* XXX should come from config1 XXX */ @@ -136,14 +136,14 @@ static inline void breakout_cerrd(unsigned int val) #ifndef CONFIG_SIBYTE_BUS_WATCHER -static void check_bus_watcher(void) -{ +static void check_bus_watcher(void) +{ uint32_t status, l2_err, memio_err; /* Destructive read, clears register and interrupt */ status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); /* Bit 31 is always on, but there's no #define for that */ - if (status & ~(1UL << 31)) { + if (status & ~(1UL << 31)) { l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS)); memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); prom_printf("Bus watcher error counters: %08x %08x\n", l2_err, memio_err); @@ -153,14 +153,14 @@ static void check_bus_watcher(void) (int)(G_SCD_BERR_TID(status) >> 6), (int)G_SCD_BERR_RID(status), (int)G_SCD_BERR_DCODE(status)); - } else { - prom_printf("Bus watcher indicates no error\n"); - } -} -#else -extern void check_bus_watcher(void); -#endif - + } else { + prom_printf("Bus watcher indicates no error\n"); + } +} +#else +extern void check_bus_watcher(void); +#endif + asmlinkage void sb1_cache_error(void) { uint64_t cerr_dpa; diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c index 9895e32b0fce..59e54f12212e 100644 --- a/arch/mips/mm/dma-noncoherent.c +++ b/arch/mips/mm/dma-noncoherent.c @@ -162,7 +162,7 @@ int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, for (i = 0; i < nents; i++, sg++) { unsigned long addr; - + addr = (unsigned long) page_address(sg->page); if (addr) __dma_sync(addr + sg->offset, sg->length, direction); @@ -230,9 +230,9 @@ void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) { unsigned long addr; - + BUG_ON(direction == DMA_NONE); - + addr = dma_handle + PAGE_OFFSET; __dma_sync(addr, size, direction); } @@ -282,9 +282,9 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction direction) { int i; - + BUG_ON(direction == DMA_NONE); - + /* Make sure that gcc doesn't leave the empty loop body. */ for (i = 0; i < nelems; i++, sg++) __dma_sync((unsigned long)page_address(sg->page), diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 9c9a271c8a3a..dc6830b10fab 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -96,7 +96,7 @@ static void __init kmap_init(void) kmap_prot = PAGE_KERNEL; } -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT static void __init fixrange_init(unsigned long start, unsigned long end, pgd_t *pgd_base) { @@ -125,7 +125,7 @@ static void __init fixrange_init(unsigned long start, unsigned long end, j = 0; } } -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ #endif /* CONFIG_HIGHMEM */ #ifndef CONFIG_NEED_MULTIPLE_NODES @@ -258,7 +258,7 @@ void __init mem_init(void) #ifdef CONFIG_BLK_DEV_INITRD void free_initrd_mem(unsigned long start, unsigned long end) { -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* Switch from KSEG0 to XKPHYS addresses */ start = (unsigned long)phys_to_virt(CPHYSADDR(start)); end = (unsigned long)phys_to_virt(CPHYSADDR(end)); @@ -286,7 +286,7 @@ void free_initmem(void) addr = (unsigned long) &__init_begin; while (addr < (unsigned long) &__init_end) { -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT page = PAGE_OFFSET | CPHYSADDR(addr); #else page = addr; diff --git a/arch/mips/mm/pg-sb1.c b/arch/mips/mm/pg-sb1.c index 59d131b5e536..1b6df7133c1e 100644 --- a/arch/mips/mm/pg-sb1.c +++ b/arch/mips/mm/pg-sb1.c @@ -114,7 +114,7 @@ static inline void copy_page_cpu(void *to, void *from) " pref " SB1_PREF_STORE_STREAMED_HINT ", -64(%1)\n" " pref " SB1_PREF_LOAD_STREAMED_HINT ", -32(%0)\n" "1: pref " SB1_PREF_STORE_STREAMED_HINT ", -32(%1)\n" -# ifdef CONFIG_MIPS64 +# ifdef CONFIG_64BIT " ld $8, -128(%0) \n" /* Block copy a cacheline */ " ld $9, -120(%0) \n" " ld $10, -112(%0) \n" @@ -148,7 +148,7 @@ static inline void copy_page_cpu(void *to, void *from) " daddiu %0, %0, -128 \n" " daddiu %1, %1, -128 \n" #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT " ld $8, 0(%0) \n" /* Block copy a cacheline */ "1: ld $9, 8(%0) \n" " ld $10, 16(%0) \n" @@ -178,7 +178,7 @@ static inline void copy_page_cpu(void *to, void *from) " daddiu %0, %0, 32 \n" " daddiu %1, %1, 32 \n" " bnel %0, %2, 1b \n" -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT " ld $8, 0(%0) \n" #else " lw $2, 0(%0) \n" @@ -186,7 +186,7 @@ static inline void copy_page_cpu(void *to, void *from) " .set pop \n" : "+r" (src), "+r" (dst) : "r" (end) -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT : "$8","$9","$10","$11","memory"); #else : "$2","$3","$6","$7","$8","$9","$10","$11","memory"); @@ -198,7 +198,7 @@ static inline void copy_page_cpu(void *to, void *from) /* * Pad descriptors to cacheline, since each is exclusively owned by a - * particular CPU. + * particular CPU. */ typedef struct dmadscr_s { u64 dscr_a; diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 87e229f4d3d5..6569be3983c7 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -448,7 +448,7 @@ L_LA(_r3000_write_probe_fail) L_LA(_r3000_write_probe_ok) /* convenience macros for instructions */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT # define i_LW(buf, rs, rt, off) i_ld(buf, rs, rt, off) # define i_SW(buf, rs, rt, off) i_sd(buf, rs, rt, off) # define i_SLL(buf, rs, rt, sh) i_dsll(buf, rs, rt, sh) @@ -486,7 +486,7 @@ L_LA(_r3000_write_probe_ok) #define i_ssnop(buf) i_sll(buf, 0, 0, 1) #define i_ehb(buf) i_sll(buf, 0, 0, 3) -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT static __init int __attribute__((unused)) in_compat_space_p(long addr) { /* Is this address in 32bit compat space? */ @@ -516,7 +516,7 @@ static __init int rel_lo(long val) static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr) { -#if CONFIG_MIPS64 +#ifdef CONFIG_64BIT if (!in_compat_space_p(addr)) { i_lui(buf, rs, rel_highest(addr)); if (rel_higher(addr)) @@ -682,7 +682,7 @@ static void il_bgezl(u32 **p, struct reloc **r, unsigned int reg, #define C0_EPC 14 #define C0_XCONTEXT 20 -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_XCONTEXT) #else # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_CONTEXT) @@ -923,7 +923,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l, } } -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* * TMP and PTR are scratch. * TMP will be clobbered, PTR will hold the pmd entry. @@ -1010,7 +1010,7 @@ build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r, } } -#else /* !CONFIG_MIPS64 */ +#else /* !CONFIG_64BIT */ /* * TMP and PTR are scratch. @@ -1038,7 +1038,7 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ } -#endif /* !CONFIG_MIPS64 */ +#endif /* !CONFIG_64BIT */ static __init void build_adjust_context(u32 **p, unsigned int ctx) { @@ -1159,7 +1159,7 @@ static void __init build_r4000_tlb_refill_handler(void) /* No need for i_nop */ } -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ #else build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ @@ -1171,7 +1171,7 @@ static void __init build_r4000_tlb_refill_handler(void) l_leave(&l, p); i_eret(&p); /* return from trap */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT build_get_pgd_vmalloc64(&p, &l, &r, K0, K1); #endif @@ -1182,7 +1182,7 @@ static void __init build_r4000_tlb_refill_handler(void) * need three, with the the second nop'ed and the third being * unused. */ -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT if ((p - tlb_handler) > 64) panic("TLB refill handler space exceeded"); #else @@ -1195,12 +1195,12 @@ static void __init build_r4000_tlb_refill_handler(void) /* * Now fold the handler in the TLB refill handler space. */ -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT f = final_handler; /* Simplest case, just copy the handler. */ copy_handler(relocs, labels, tlb_handler, p, f); final_len = p - tlb_handler; -#else /* CONFIG_MIPS64 */ +#else /* CONFIG_64BIT */ f = final_handler + 32; if ((p - tlb_handler) <= 32) { /* Just copy the handler. */ @@ -1235,7 +1235,7 @@ static void __init build_r4000_tlb_refill_handler(void) copy_handler(relocs, labels, split, p, final_handler); final_len = (f - (final_handler + 32)) + (p - split); } -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ resolve_relocs(relocs, labels); printk("Synthesized TLB refill handler (%u instructions).\n", @@ -1605,7 +1605,7 @@ build_r4000_tlbchange_handler_head(u32 **p, struct label **l, struct reloc **r, unsigned int pte, unsigned int ptr) { -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */ #else build_get_pgde32(p, pte, ptr); /* get pgd in ptr */ @@ -1636,7 +1636,7 @@ build_r4000_tlbchange_handler_tail(u32 **p, struct label **l, l_leave(l, *p); i_eret(p); /* return from trap */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT build_get_pgd_vmalloc64(p, l, r, tmp, ptr); #endif } diff --git a/arch/mips/momentum/jaguar_atx/int-handler.S b/arch/mips/momentum/jaguar_atx/int-handler.S index 43fd5a58077c..55bc789733f2 100644 --- a/arch/mips/momentum/jaguar_atx/int-handler.S +++ b/arch/mips/momentum/jaguar_atx/int-handler.S @@ -27,11 +27,11 @@ SAVE_ALL CLI .set at - mfc0 t0, CP0_CAUSE + mfc0 t0, CP0_CAUSE mfc0 t2, CP0_STATUS and t0, t2 - + andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */ bnez t1, ll_sw0_irq andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */ @@ -103,25 +103,25 @@ ll_pcia_irq: move a1, sp jal do_IRQ j ret_from_irq - + ll_pcib_irq: li a0, 5 move a1, sp jal do_IRQ j ret_from_irq - + ll_uart_irq: li a0, 6 move a1, sp jal do_IRQ j ret_from_irq - + ll_cputimer_irq: li a0, 7 move a1, sp jal ll_timer_interrupt j ret_from_irq - + ll_mv64340_decode_irq: move a0, sp jal ll_mv64340_irq diff --git a/arch/mips/momentum/jaguar_atx/prom.c b/arch/mips/momentum/jaguar_atx/prom.c index fa5982ac0ac6..14ae2e713585 100644 --- a/arch/mips/momentum/jaguar_atx/prom.c +++ b/arch/mips/momentum/jaguar_atx/prom.c @@ -64,7 +64,7 @@ static u8 exchange_bit(u8 val, u8 cs) /* turn the clock off and read-strobe */ JAGUAR_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE); - + /* return the data */ return ((JAGUAR_FPGA_READ(EEPROM_MODE) >> 3) & 0x1); } @@ -90,7 +90,7 @@ void get_mac(char dest[6]) } #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT unsigned long signext(unsigned long addr) { @@ -143,7 +143,7 @@ char *arg64(unsigned long addrin, int arg_index) return p; } -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ /* PMON passes arguments in C main() style */ void __init prom_init(void) @@ -158,7 +158,7 @@ void __init prom_init(void) // ja_setup_console(); /* The very first thing. */ #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT char *ptr; printk("Mips64 Jaguar-ATX\n"); @@ -201,7 +201,7 @@ void __init prom_init(void) } printk("arcs_cmdline: %s\n", arcs_cmdline); -#else /* CONFIG_MIPS64 */ +#else /* CONFIG_64BIT */ /* save the PROM vectors for debugging use */ debug_vectors = cv; @@ -226,7 +226,7 @@ void __init prom_init(void) } env++; } -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ mips_machgroup = MACH_GROUP_MOMENCO; mips_machtype = MACH_MOMENCO_JAGUAR_ATX; diff --git a/arch/mips/momentum/jaguar_atx/reset.c b/arch/mips/momentum/jaguar_atx/reset.c index 48039484cdf9..c4236b1e59fa 100644 --- a/arch/mips/momentum/jaguar_atx/reset.c +++ b/arch/mips/momentum/jaguar_atx/reset.c @@ -27,7 +27,7 @@ void momenco_jaguar_restart(char *command) { /* base address of timekeeper portion of part */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT void *nvram = (void*) 0xfffffffffc807000; #else void *nvram = (void*) 0xfc807000; diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c index 30462e715066..90288cf2b1e0 100644 --- a/arch/mips/momentum/jaguar_atx/setup.c +++ b/arch/mips/momentum/jaguar_atx/setup.c @@ -105,7 +105,7 @@ void __init bus_error_init(void) { /* nothing */ } static __init void wire_stupidity_into_tlb(void) { -#ifdef CONFIG_MIPS32 +#ifdef CONFIG_32BIT write_c0_wired(0); local_flush_tlb_all(); @@ -451,7 +451,7 @@ static int __init momenco_jaguar_atx_setup(void) #ifdef GEMDEBUG_TRACEBUFFER { unsigned int tbControl; - tbControl = + tbControl = 0 << 26 | /* post trigger delay 0 */ 0x2 << 16 | /* sequential trace mode */ // 0x0 << 16 | /* non-sequential trace mode */ diff --git a/arch/mips/momentum/ocelot_3/prom.c b/arch/mips/momentum/ocelot_3/prom.c index 89c17a0c0bed..c4fa9c525faa 100644 --- a/arch/mips/momentum/ocelot_3/prom.c +++ b/arch/mips/momentum/ocelot_3/prom.c @@ -93,7 +93,7 @@ void get_mac(char dest[6]) #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT unsigned long signext(unsigned long addr) { @@ -145,7 +145,7 @@ char *arg64(unsigned long addrin, int arg_index) return p; } -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ void __init prom_init(void) { @@ -155,7 +155,7 @@ void __init prom_init(void) struct callvectors *cv = (struct callvectors *) fw_arg3; int i; -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT char *ptr; printk("prom_init - MIPS64\n"); @@ -198,7 +198,7 @@ void __init prom_init(void) } printk("arcs_cmdline: %s\n", arcs_cmdline); -#else /* CONFIG_MIPS64 */ +#else /* CONFIG_64BIT */ /* save the PROM vectors for debugging use */ debug_vectors = cv; @@ -224,7 +224,7 @@ void __init prom_init(void) } env++; } -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ mips_machgroup = MACH_GROUP_MOMENCO; mips_machtype = MACH_MOMENCO_OCELOT_3; @@ -234,7 +234,7 @@ void __init prom_init(void) get_mac(prom_mac_addr_base); #endif -#ifndef CONFIG_MIPS64 +#ifndef CONFIG_64BIT debug_vectors->printf("Booting Linux kernel...\n"); #endif } diff --git a/arch/mips/momentum/ocelot_c/int-handler.S b/arch/mips/momentum/ocelot_c/int-handler.S index 2f2430648abc..52349d9bf1be 100644 --- a/arch/mips/momentum/ocelot_c/int-handler.S +++ b/arch/mips/momentum/ocelot_c/int-handler.S @@ -27,11 +27,11 @@ SAVE_ALL CLI .set at - mfc0 t0, CP0_CAUSE + mfc0 t0, CP0_CAUSE mfc0 t2, CP0_STATUS and t0, t2 - + andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */ bnez t1, ll_sw0_irq andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */ @@ -83,7 +83,7 @@ ll_pmc_irq: move a1, sp jal do_IRQ j ret_from_irq - + ll_cpci_decode_irq: move a0, sp jal ll_cpci_irq @@ -99,4 +99,4 @@ ll_cputimer_irq: move a1, sp jal do_IRQ j ret_from_irq - + diff --git a/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h b/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h index a6cf7a7959b3..97fb77dad723 100644 --- a/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h +++ b/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h @@ -32,7 +32,7 @@ #include <linux/config.h> -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define OCELOT_C_CS0_ADDR (0xfffffffffc000000) #else #define OCELOT_C_CS0_ADDR (0xfc000000) diff --git a/arch/mips/momentum/ocelot_c/prom.c b/arch/mips/momentum/ocelot_c/prom.c index 49ac302d8901..5b6809724b15 100644 --- a/arch/mips/momentum/ocelot_c/prom.c +++ b/arch/mips/momentum/ocelot_c/prom.c @@ -67,7 +67,7 @@ static u8 exchange_bit(u8 val, u8 cs) /* turn the clock off and read-strobe */ OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE); - + /* return the data */ return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1); } @@ -94,7 +94,7 @@ void get_mac(char dest[6]) #endif -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT unsigned long signext(unsigned long addr) { @@ -144,7 +144,7 @@ char *arg64(unsigned long addrin, int arg_index) p = (char *)get_arg(args, arg_index); return p; } -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ void __init prom_init(void) @@ -155,7 +155,7 @@ void __init prom_init(void) struct callvectors *cv = (struct callvectors *) fw_arg3; int i; -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT char *ptr; printk("prom_init - MIPS64\n"); @@ -197,7 +197,7 @@ void __init prom_init(void) } printk("arcs_cmdline: %s\n", arcs_cmdline); -#else /* CONFIG_MIPS64 */ +#else /* CONFIG_64BIT */ /* save the PROM vectors for debugging use */ debug_vectors = cv; @@ -222,7 +222,7 @@ void __init prom_init(void) } env++; } -#endif /* CONFIG_MIPS64 */ +#endif /* CONFIG_64BIT */ mips_machgroup = MACH_GROUP_MOMENCO; mips_machtype = MACH_MOMENCO_OCELOT_C; @@ -232,7 +232,7 @@ void __init prom_init(void) get_mac(prom_mac_addr_base); #endif -#ifndef CONFIG_MIPS64 +#ifndef CONFIG_64BIT debug_vectors->printf("Booting Linux kernel...\n"); #endif } diff --git a/arch/mips/momentum/ocelot_c/reset.c b/arch/mips/momentum/ocelot_c/reset.c index 1f2b4263cc8c..6a2489f3b9a0 100644 --- a/arch/mips/momentum/ocelot_c/reset.c +++ b/arch/mips/momentum/ocelot_c/reset.c @@ -28,7 +28,7 @@ void momenco_ocelot_restart(char *command) { /* base address of timekeeper portion of part */ void *nvram = (void *) -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT 0xfffffffffc807000; #else 0xfc807000; diff --git a/arch/mips/momentum/ocelot_c/setup.c b/arch/mips/momentum/ocelot_c/setup.c index 021c00e3c07c..844ddd06349b 100644 --- a/arch/mips/momentum/ocelot_c/setup.c +++ b/arch/mips/momentum/ocelot_c/setup.c @@ -109,7 +109,7 @@ void PMON_v2_setup(void) */ printk("PMON_v2_setup\n"); -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT /* marvell and extra space */ add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xfffffffff4000000, PM_64K); /* fpga, rtc, and uart */ @@ -134,7 +134,7 @@ void PMON_v2_setup(void) unsigned long m48t37y_get_time(void) { -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT unsigned char *rtc_base = (unsigned char*)0xfffffffffc800000; #else unsigned char* rtc_base = (unsigned char*)0xfc800000; @@ -163,7 +163,7 @@ unsigned long m48t37y_get_time(void) int m48t37y_set_time(unsigned long sec) { -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT unsigned char* rtc_base = (unsigned char*)0xfffffffffc800000; #else unsigned char* rtc_base = (unsigned char*)0xfc800000; @@ -342,7 +342,7 @@ static void __init momenco_ocelot_c_setup(void) early_initcall(momenco_ocelot_c_setup); -#ifndef CONFIG_MIPS64 +#ifndef CONFIG_64BIT /* This needs to be one of the first initcalls, because no I/O port access can work before this */ static int io_base_ioremap(void) diff --git a/arch/mips/pci/fixup-ddb5074.c b/arch/mips/pci/fixup-ddb5074.c index b345e528a53c..5a4a7c239c42 100644 --- a/arch/mips/pci/fixup-ddb5074.c +++ b/arch/mips/pci/fixup-ddb5074.c @@ -5,7 +5,7 @@ static void ddb5074_fixup(struct pci_dev *dev) { extern struct pci_dev *pci_pmu; u8 t8; - + pci_pmu = dev; /* for LEDs D2 and D3 */ /* Program the lines for LEDs D2 and D3 to output */ pci_read_config_byte(dev, 0x7d, &t8); diff --git a/arch/mips/pci/fixup-ddb5477.c b/arch/mips/pci/fixup-ddb5477.c index 6abdc88bab1e..2f1444e60654 100644 --- a/arch/mips/pci/fixup-ddb5477.c +++ b/arch/mips/pci/fixup-ddb5477.c @@ -65,7 +65,7 @@ static void ddb5477_amd_lance_fixup(struct pci_dev *dev) ioaddr = pci_resource_start(dev, 0); inw(ioaddr + PCNET32_WIO_RESET); /* reset chip */ - + /* bcr_18 |= 0x0800 */ outw(18, ioaddr + PCNET32_WIO_RAP); temp = inw(ioaddr + PCNET32_WIO_BDP); diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c index b9296d9942b3..bf2c41d1e9c5 100644 --- a/arch/mips/pci/fixup-malta.c +++ b/arch/mips/pci/fixup-malta.c @@ -56,7 +56,7 @@ static void __init malta_piix_func0_fixup(struct pci_dev *pdev) 0, 0, 0, 3, 4, 5, 6, 7, 0, 9, 10, 11, - 12, 0, 14, 15 + 12, 0, 14, 15 }; int i; diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c index de4e443da208..ceeb1860895a 100644 --- a/arch/mips/pci/fixup-rbtx4927.c +++ b/arch/mips/pci/fixup-rbtx4927.c @@ -7,7 +7,7 @@ * Author: MontaVista Software, Inc. * ppopov@mvista.com or source@mvista.com * - * Copyright (C) 2000-2001 Toshiba Corporation + * Copyright (C) 2000-2001 Toshiba Corporation * * Copyright (C) 2004 MontaVista Software Inc. * Author: Manish Lachwani (mlachwani@mvista.com) diff --git a/arch/mips/pci/fixup-sni.c b/arch/mips/pci/fixup-sni.c index c8ef01a017cc..a176f2ca8656 100644 --- a/arch/mips/pci/fixup-sni.c +++ b/arch/mips/pci/fixup-sni.c @@ -32,7 +32,7 @@ * Device 4: Unused * Device 5: Slot 2 * Device 6: Slot 3 - * Device 7: Slot 4 + * Device 7: Slot 4 * * Documentation says the VGA is device 5 and device 3 is unused but that * seem to be a documentation error. At least on my RM200C the Cirrus diff --git a/arch/mips/pci/fixup-tb0219.c b/arch/mips/pci/fixup-tb0219.c index 850a900f0eb4..bc55b06e1904 100644 --- a/arch/mips/pci/fixup-tb0219.c +++ b/arch/mips/pci/fixup-tb0219.c @@ -29,27 +29,12 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) switch (slot) { case 12: - vr41xx_set_irq_trigger(TB0219_PCI_SLOT1_PIN, - TRIGGER_LEVEL, - SIGNAL_THROUGH); - vr41xx_set_irq_level(TB0219_PCI_SLOT1_PIN, - LEVEL_LOW); irq = TB0219_PCI_SLOT1_IRQ; break; case 13: - vr41xx_set_irq_trigger(TB0219_PCI_SLOT2_PIN, - TRIGGER_LEVEL, - SIGNAL_THROUGH); - vr41xx_set_irq_level(TB0219_PCI_SLOT2_PIN, - LEVEL_LOW); irq = TB0219_PCI_SLOT2_IRQ; break; case 14: - vr41xx_set_irq_trigger(TB0219_PCI_SLOT3_PIN, - TRIGGER_LEVEL, - SIGNAL_THROUGH); - vr41xx_set_irq_level(TB0219_PCI_SLOT3_PIN, - LEVEL_LOW); irq = TB0219_PCI_SLOT3_IRQ; break; default: diff --git a/arch/mips/pci/ops-ddb5477.c b/arch/mips/pci/ops-ddb5477.c index e955443fedf9..0406b50a37d8 100644 --- a/arch/mips/pci/ops-ddb5477.c +++ b/arch/mips/pci/ops-ddb5477.c @@ -127,7 +127,7 @@ static inline void ddb_close_config_base(struct pci_config_swap *swap) } static int read_config_dword(struct pci_config_swap *swap, - struct pci_bus *bus, u32 devfn, u32 where, + struct pci_bus *bus, u32 devfn, u32 where, u32 * val) { u32 bus_num, slot_num, func_num; @@ -153,7 +153,7 @@ static int read_config_dword(struct pci_config_swap *swap, } static int read_config_word(struct pci_config_swap *swap, - struct pci_bus *bus, u32 devfn, u32 where, + struct pci_bus *bus, u32 devfn, u32 where, u16 * val) { int status; diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c index 2a9d7227fe87..7688b7711329 100644 --- a/arch/mips/pci/ops-tx4927.c +++ b/arch/mips/pci/ops-tx4927.c @@ -1,16 +1,16 @@ /* * Copyright 2001 MontaVista Software Inc. * Author: MontaVista Software, Inc. - * ahennessy@mvista.com + * ahennessy@mvista.com * - * Copyright (C) 2000-2001 Toshiba Corporation + * Copyright (C) 2000-2001 Toshiba Corporation * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) * * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c * * Define the pci_ops for the Toshiba rbtx4927 * - * Much of the code is derived from the original DDB5074 port by + * Much of the code is derived from the original DDB5074 port by * Geert Uytterhoeven <geert@sonycom.com> * * Copyright 2004 MontaVista Software Inc. diff --git a/arch/mips/pci/pci-ddb5477.c b/arch/mips/pci/pci-ddb5477.c index 4ddd53eaf656..826d653184e5 100644 --- a/arch/mips/pci/pci-ddb5477.c +++ b/arch/mips/pci/pci-ddb5477.c @@ -76,7 +76,7 @@ struct pci_controller ddb5477_io_controller = { */ /* - * irq mapping : device -> pci int # -> vrc4377 irq# , + * irq mapping : device -> pci int # -> vrc4377 irq# , * ddb5477 board manual page 4 and vrc5477 manual page 46 */ @@ -137,9 +137,9 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) unsigned char *slot_irq_map; unsigned char irq; - /* + /* * We ignore the swizzled slot and pin values. The original - * pci_fixup_irq() codes largely base irq number on the dev slot + * pci_fixup_irq() codes largely base irq number on the dev slot * numbers because except for one case they are unique even * though there are multiple pci buses. */ @@ -160,7 +160,7 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) if (mips_machtype == MACH_NEC_ROCKHOPPERII) { /* hack to distinquish overlapping slot 20s, one - * on bus 0 (ALI USB on the M1535 on the backplane), + * on bus 0 (ALI USB on the M1535 on the backplane), * and one on bus 2 (NEC USB controller on the CPU board) * Make the M1535 USB - ISA IRQ number 9. */ diff --git a/arch/mips/pci/pci-ip32.c b/arch/mips/pci/pci-ip32.c index 1faeb034f06e..000dc6af6cd3 100644 --- a/arch/mips/pci/pci-ip32.c +++ b/arch/mips/pci/pci-ip32.c @@ -84,7 +84,7 @@ static irqreturn_t macepci_error(int irq, void *dev, struct pt_regs *regs) extern struct pci_ops mace_pci_ops; -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT static struct resource mace_pci_mem_resource = { .name = "SGI O2 PCI MEM", .start = MACEPCI_HI_MEMORY, diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 8141dffac241..a8d499b0a36f 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -132,7 +132,7 @@ static int __init pcibios_init(void) hose->need_domain_info = need_domain_info; next_busno = bus->subordinate + 1; /* Don't allow 8-bit bus number overflow inside the hose - - reserve some space for bridges. */ + reserve some space for bridges. */ if (next_busno > 224) { next_busno = 0; need_domain_info = 1; @@ -260,7 +260,7 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus) (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { pci_read_bridge_bases(bus); pcibios_fixup_device_resources(dev, bus); - } + } for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { struct pci_dev *dev = pci_dev_b(ln); @@ -292,8 +292,25 @@ pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, region->end = res->end - offset; } +void __devinit +pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, + struct pci_bus_region *region) +{ + struct pci_controller *hose = (struct pci_controller *)dev->sysdata; + unsigned long offset = 0; + + if (res->flags & IORESOURCE_IO) + offset = hose->io_offset; + else if (res->flags & IORESOURCE_MEM) + offset = hose->mem_offset; + + res->start = region->start + offset; + res->end = region->end + offset; +} + #ifdef CONFIG_HOTPLUG EXPORT_SYMBOL(pcibios_resource_to_bus); +EXPORT_SYMBOL(pcibios_bus_to_resource); EXPORT_SYMBOL(PCIBIOS_MIN_IO); EXPORT_SYMBOL(PCIBIOS_MIN_MEM); #endif diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c index b067988614c3..97862f45496d 100644 --- a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c +++ b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c @@ -30,7 +30,7 @@ * * This code reads the ATMEL 24CXX EEPROM. The PMC-Sierra Yosemite board uses the ATMEL * 24C32/24C64 which uses two byte addressing as compared to 24C16. Note that this program - * uses the serial port like /dev/ttyS0, to communicate with the EEPROM. Hence, you are + * uses the serial port like /dev/ttyS0, to communicate with the EEPROM. Hence, you are * expected to have a connectivity from the EEPROM to the serial port. This program does * __not__ communicate using the I2C protocol */ @@ -64,14 +64,14 @@ static void send_ack(void) static void send_byte(unsigned char byte) { int i = 0; - - for (i = 7; i >= 0; i--) + + for (i = 7; i >= 0; i--) send_bit((byte >> i) & 0x01); } - + static void send_start(void) { - sda_hi; + sda_hi; delay(TXX); scl_hi; delay(TXX); @@ -114,9 +114,9 @@ static unsigned char recv_byte(void) { int i; unsigned char byte=0; - for (i=7;i>=0;i--) + for (i=7;i>=0;i--) byte |= (recv_bit() << i); - + return byte; } diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h index d27566d99ffc..c19f01a32045 100644 --- a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h +++ b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h @@ -27,7 +27,7 @@ */ /* - * Header file for atmel_read_eeprom.c + * Header file for atmel_read_eeprom.c */ #include <linux/types.h> @@ -46,7 +46,7 @@ #define DEFAULT_PORT "/dev/ttyS0" /* Port to open */ #define TXX 0 /* Dummy loop for spinning */ -#define BLOCK_SEL 0x00 +#define BLOCK_SEL 0x00 #define SLAVE_ADDR 0xa0 #define READ_BIT 0x01 #define WRITE_BIT 0x00 diff --git a/arch/mips/qemu/Makefile b/arch/mips/qemu/Makefile new file mode 100644 index 000000000000..934944ab9e85 --- /dev/null +++ b/arch/mips/qemu/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for Qemu specific kernel interface routines under Linux. +# + +obj-y = q-firmware.o q-int.o q-irq.o q-mem.o q-setup.o diff --git a/arch/mips/qemu/q-firmware.c b/arch/mips/qemu/q-firmware.c new file mode 100644 index 000000000000..5980f02b2df9 --- /dev/null +++ b/arch/mips/qemu/q-firmware.c @@ -0,0 +1,7 @@ +#include <linux/init.h> +#include <asm/bootinfo.h> + +void __init prom_init(void) +{ + add_memory_region(0x0<<20, 0x10<<20, BOOT_MEM_RAM); +} diff --git a/arch/mips/qemu/q-int.S b/arch/mips/qemu/q-int.S new file mode 100644 index 000000000000..6e3dfe5eb14b --- /dev/null +++ b/arch/mips/qemu/q-int.S @@ -0,0 +1,17 @@ +/* + * Qemu interrupt handler code. + * + * Copyright (C) 2005 by Ralf Baechle + */ +#include <asm/asm.h> +#include <asm/regdef.h> +#include <asm/stackframe.h> + + .align 5 + NESTED(qemu_handle_int, PT_SIZE, sp) + SAVE_ALL + CLI + move a0, sp + PTR_LA ra, ret_from_irq + j do_qemu_int + END(qemu_handle_int) diff --git a/arch/mips/qemu/q-irq.c b/arch/mips/qemu/q-irq.c new file mode 100644 index 000000000000..2c4e0704ff10 --- /dev/null +++ b/arch/mips/qemu/q-irq.c @@ -0,0 +1,37 @@ +#include <linux/init.h> +#include <linux/linkage.h> + +#include <asm/i8259.h> +#include <asm/mipsregs.h> +#include <asm/qemu.h> +#include <asm/system.h> +#include <asm/time.h> + +extern asmlinkage void qemu_handle_int(void); + +asmlinkage void do_qemu_int(struct pt_regs *regs) +{ + unsigned int pending = read_c0_status() & read_c0_cause(); + + if (pending & 0x8000) { + ll_timer_interrupt(Q_COUNT_COMPARE_IRQ, regs); + return; + } + if (pending & 0x0400) { + int irq = i8259_irq(); + + if (likely(irq >= 0)) + do_IRQ(irq, regs); + + return; + } +} + +void __init arch_init_irq(void) +{ + set_except_vector(0, qemu_handle_int); + mips_hpt_frequency = QEMU_C0_COUNTER_CLOCK; /* 100MHz */ + + init_i8259_irqs(); + set_c0_status(0x8400); +} diff --git a/arch/mips/qemu/q-mem.c b/arch/mips/qemu/q-mem.c new file mode 100644 index 000000000000..d174fac43031 --- /dev/null +++ b/arch/mips/qemu/q-mem.c @@ -0,0 +1,6 @@ +#include <linux/init.h> + +unsigned long __init prom_free_prom_memory(void) +{ + return 0UL; +} diff --git a/arch/mips/qemu/q-setup.c b/arch/mips/qemu/q-setup.c new file mode 100644 index 000000000000..1a80eee8cd35 --- /dev/null +++ b/arch/mips/qemu/q-setup.c @@ -0,0 +1,20 @@ +#include <linux/init.h> +#include <asm/io.h> +#include <asm/time.h> + +#define QEMU_PORT_BASE 0xb4000000 + +static void __init qemu_timer_setup(struct irqaction *irq) +{ + /* set the clock to 100 Hz */ + outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */ + outb_p(LATCH & 0xff , 0x40); /* LSB */ + outb(LATCH >> 8 , 0x40); /* MSB */ + setup_irq(0, irq); +} + +void __init plat_setup(void) +{ + set_io_port_base(QEMU_PORT_BASE); + board_timer_setup = qemu_timer_setup; +} diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c index 0ab4abf65d58..fa0e719c5bd1 100644 --- a/arch/mips/sgi-ip22/ip22-eisa.c +++ b/arch/mips/sgi-ip22/ip22-eisa.c @@ -242,7 +242,7 @@ int __init ip22_eisa_init(void) int i, c; char *str; u8 *slot_addr; - + if (!(sgimc->systemid & SGIMC_SYSID_EPRESENT)) { printk(KERN_INFO "EISA: bus not present.\n"); return 1; diff --git a/arch/mips/sgi-ip22/ip22-hpc.c b/arch/mips/sgi-ip22/ip22-hpc.c index c0afeccb08c4..5c00cdd20d8e 100644 --- a/arch/mips/sgi-ip22/ip22-hpc.c +++ b/arch/mips/sgi-ip22/ip22-hpc.c @@ -49,7 +49,7 @@ void __init sgihpc_init(void) sgint = &sgioc->int3; system_type = "SGI Indy"; } - + sgi_ioc_reset = (SGIOC_RESET_PPORT | SGIOC_RESET_KBDMOUSE | SGIOC_RESET_EISA | SGIOC_RESET_ISDN | SGIOC_RESET_LC0OFF); diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c index ea2844d29e6e..d16fb43b1a93 100644 --- a/arch/mips/sgi-ip22/ip22-int.c +++ b/arch/mips/sgi-ip22/ip22-int.c @@ -28,7 +28,7 @@ /* #define DEBUG_SGINT */ /* So far nothing hangs here */ -#undef USE_LIO3_IRQ +#undef USE_LIO3_IRQ struct sgint_regs *sgint; @@ -272,32 +272,32 @@ void indy_buserror_irq(struct pt_regs *regs) irq_exit(); } -static struct irqaction local0_cascade = { +static struct irqaction local0_cascade = { .handler = no_action, .flags = SA_INTERRUPT, .name = "local0 cascade", }; -static struct irqaction local1_cascade = { +static struct irqaction local1_cascade = { .handler = no_action, .flags = SA_INTERRUPT, .name = "local1 cascade", }; -static struct irqaction buserr = { +static struct irqaction buserr = { .handler = no_action, .flags = SA_INTERRUPT, .name = "Bus Error", }; -static struct irqaction map0_cascade = { +static struct irqaction map0_cascade = { .handler = no_action, .flags = SA_INTERRUPT, .name = "mapable0 cascade", }; #ifdef USE_LIO3_IRQ -static struct irqaction map1_cascade = { +static struct irqaction map1_cascade = { .handler = no_action, .flags = SA_INTERRUPT, .name = "mapable1 cascade", diff --git a/arch/mips/sgi-ip22/ip22-nvram.c b/arch/mips/sgi-ip22/ip22-nvram.c index de43e86fa17c..fd29fd407ae8 100644 --- a/arch/mips/sgi-ip22/ip22-nvram.c +++ b/arch/mips/sgi-ip22/ip22-nvram.c @@ -39,7 +39,7 @@ *ptr |= EEPROM_CSEL; \ *ptr |= EEPROM_ECLK; }) - + #define eeprom_cs_off(ptr) ({ \ *ptr &= ~EEPROM_ECLK; \ *ptr &= ~EEPROM_CSEL; \ @@ -50,7 +50,7 @@ /* * clock in the nvram command and the register number. For the * national semiconductor nv ram chip the op code is 3 bits and - * the address is 6/8 bits. + * the address is 6/8 bits. */ static inline void eeprom_cmd(volatile unsigned int *ctrl, unsigned cmd, unsigned reg) @@ -90,7 +90,7 @@ unsigned short ip22_eeprom_read(volatile unsigned int *ctrl, int reg) if (*ctrl & EEPROM_DATI) res |= 1; } - + eeprom_cs_off(ctrl); return res; @@ -113,7 +113,7 @@ unsigned short ip22_nvram_read(int reg) reg <<= 1; tmp = hpc3c0->bbram[reg++] & 0xff; return (tmp << 8) | (hpc3c0->bbram[reg] & 0xff); - } + } } EXPORT_SYMBOL(ip22_nvram_read); diff --git a/arch/mips/sgi-ip22/ip22-reset.c b/arch/mips/sgi-ip22/ip22-reset.c index ed5c60adce63..214ffd2e98a3 100644 --- a/arch/mips/sgi-ip22/ip22-reset.c +++ b/arch/mips/sgi-ip22/ip22-reset.c @@ -185,7 +185,7 @@ static irqreturn_t panel_int(int irq, void *dev_id, struct pt_regs *regs) add_timer(&debounce_timer); } - /* Power button was pressed + /* Power button was pressed * ioc.ps page 22: "The Panel Register is called Power Control by Full * House. Only lowest 2 bits are used. Guiness uses upper four bits * for volume control". This is not true, all bits are pulled high diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c index 173f76805ea3..df9b5694328a 100644 --- a/arch/mips/sgi-ip22/ip22-time.c +++ b/arch/mips/sgi-ip22/ip22-time.c @@ -126,7 +126,7 @@ static __init void indy_time_init(void) unsigned long r4k_ticks[3]; unsigned long r4k_tick; - /* + /* * Figure out the r4k offset, the algorithm is very simple and works in * _all_ cases as long as the 8254 counter register itself works ok (as * an interrupt driving timer it does not because of bug, this is why diff --git a/arch/mips/sgi-ip27/ip27-memory.c b/arch/mips/sgi-ip27/ip27-memory.c index a160d04f7dbe..ef20d9ac0ba3 100644 --- a/arch/mips/sgi-ip27/ip27-memory.c +++ b/arch/mips/sgi-ip27/ip27-memory.c @@ -538,7 +538,7 @@ void __init mem_init(void) for_each_online_node(node) { unsigned slot, numslots; struct page *end, *p; - + /* * This will free up the bootmem, ie, slot 0 memory. */ diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index 8c1b96fffa76..cddf1cedf007 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c @@ -118,7 +118,7 @@ again: * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be * called as close as possible to when a second starts. */ - if ((time_status & STA_UNSYNC) == 0 && + if (ntp_synced() && xtime.tv_sec > last_rtc_update + 660 && (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 && (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) { diff --git a/arch/mips/sgi-ip32/ip32-reset.c b/arch/mips/sgi-ip32/ip32-reset.c index 281f090e48a4..88e1f52059ff 100644 --- a/arch/mips/sgi-ip32/ip32-reset.c +++ b/arch/mips/sgi-ip32/ip32-reset.c @@ -140,7 +140,7 @@ static irqreturn_t ip32_rtc_int(int irq, void *dev_id, struct pt_regs *regs) reg_c = CMOS_READ(RTC_INTR_FLAGS); if (!(reg_c & RTC_IRQF)) { - printk(KERN_WARNING + printk(KERN_WARNING "%s: RTC IRQ without RTC_IRQF\n", __FUNCTION__); } /* Wait until interrupt goes away */ diff --git a/arch/mips/sibyte/cfe/cfe_error.h b/arch/mips/sibyte/cfe/cfe_error.h index 77eb4935bfb4..975f00002cbe 100644 --- a/arch/mips/sibyte/cfe/cfe_error.h +++ b/arch/mips/sibyte/cfe/cfe_error.h @@ -17,15 +17,15 @@ */ /* ********************************************************************* - * + * * Broadcom Common Firmware Environment (CFE) - * + * * Error codes File: cfe_error.h - * + * * CFE's global error code list is here. - * + * * Author: Mitch Lichtenberg - * + * ********************************************************************* */ diff --git a/arch/mips/sibyte/cfe/console.c b/arch/mips/sibyte/cfe/console.c index 53a5c1eb5611..7721100d0275 100644 --- a/arch/mips/sibyte/cfe/console.c +++ b/arch/mips/sibyte/cfe/console.c @@ -38,7 +38,7 @@ static void cfe_console_write(struct console *cons, const char *str, last += written; } while (last < count); } - + } static int cfe_console_setup(struct console *cons, char *str) diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/cfe/setup.c index d6d0364fa760..7a2c7a8510d4 100644 --- a/arch/mips/sibyte/cfe/setup.c +++ b/arch/mips/sibyte/cfe/setup.c @@ -33,7 +33,7 @@ #include "cfe_error.h" /* Max ram addressable in 32-bit segments */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT #define MAX_RAM_SIZE (~0ULL) #else #ifdef CONFIG_HIGHMEM @@ -285,7 +285,7 @@ void __init prom_init(void) while (1) ; } cfe_init(cfe_handle, cfe_ept); - /* + /* * Get the handle for (at least) prom_putchar, possibly for * boot console */ diff --git a/arch/mips/sibyte/cfe/smp.c b/arch/mips/sibyte/cfe/smp.c index 73392190d2b1..e44ce1a9eea9 100644 --- a/arch/mips/sibyte/cfe/smp.c +++ b/arch/mips/sibyte/cfe/smp.c @@ -57,7 +57,7 @@ void __init prom_prepare_cpus(unsigned int max_cpus) void prom_boot_secondary(int cpu, struct task_struct *idle) { int retval; - + retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap, __KSTK_TOS(idle), (unsigned long)idle->thread_info, 0); diff --git a/arch/mips/sibyte/sb1250/bus_watcher.c b/arch/mips/sibyte/sb1250/bus_watcher.c index 182a16f42e2d..1a97e3127aeb 100644 --- a/arch/mips/sibyte/sb1250/bus_watcher.c +++ b/arch/mips/sibyte/sb1250/bus_watcher.c @@ -10,13 +10,13 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* +/* * The Bus Watcher monitors internal bus transactions and maintains * counts of transactions with error status, logging details and * causing one of several interrupts. This driver provides a handler @@ -155,7 +155,7 @@ static int bw_read_proc(char *page, char **start, off_t off, static void create_proc_decoder(struct bw_stats_struct *stats) { struct proc_dir_entry *ent; - + ent = create_proc_read_entry("bus_watcher", S_IWUSR | S_IRUGO, NULL, bw_read_proc, stats); if (!ent) { diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index 2728abbc94d2..2725b263cced 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c @@ -377,7 +377,7 @@ void __init arch_init_irq(void) /* * Note that the timer interrupts are also mapped, but this is - * done in sb1250_time_init(). Also, the profiling driver + * done in sb1250_time_init(). Also, the profiling driver * does its own management of IP7. */ @@ -392,7 +392,7 @@ void __init arch_init_irq(void) if (kgdb_flag) { kgdb_irq = K_INT_UART_0 + kgdb_port; -#ifdef CONFIG_SIBYTE_SB1250_DUART +#ifdef CONFIG_SIBYTE_SB1250_DUART sb1250_duart_present[kgdb_port] = 0; #endif /* Setup uart 1 settings, mapper */ diff --git a/arch/mips/sibyte/swarm/rtc_m41t81.c b/arch/mips/sibyte/swarm/rtc_m41t81.c index 0e633ee8d83c..a686bb716ec6 100644 --- a/arch/mips/sibyte/swarm/rtc_m41t81.c +++ b/arch/mips/sibyte/swarm/rtc_m41t81.c @@ -128,7 +128,7 @@ static int m41t81_write(uint8_t addr, int b) /* Clear error bit by writing a 1 */ bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; - } + } /* read the same byte again to make sure it is written */ bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, @@ -136,7 +136,7 @@ static int m41t81_write(uint8_t addr, int b) while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; - + return 0; } @@ -148,13 +148,13 @@ int m41t81_set_time(unsigned long t) /* * Note the write order matters as it ensures the correctness. - * When we write sec, 10th sec is clear. It is reasonable to + * When we write sec, 10th sec is clear. It is reasonable to * believe we should finish writing min within a second. */ tm.tm_sec = BIN2BCD(tm.tm_sec); m41t81_write(M41T81REG_SC, tm.tm_sec); - + tm.tm_min = BIN2BCD(tm.tm_min); m41t81_write(M41T81REG_MN, tm.tm_min); @@ -187,7 +187,7 @@ unsigned long m41t81_get_time(void) { unsigned int year, mon, day, hour, min, sec; - /* + /* * min is valid if two reads of sec are the same. */ for (;;) { diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c index 457aeb7be858..4daeaa413def 100644 --- a/arch/mips/sibyte/swarm/setup.c +++ b/arch/mips/sibyte/swarm/setup.c @@ -73,7 +73,7 @@ int swarm_be_handler(struct pt_regs *regs, int is_fixup) { if (!is_fixup && (regs->cp0_cause & 4)) { /* Data bus error - print PA */ -#ifdef CONFIG_MIPS64 +#ifdef CONFIG_64BIT printk("DBE physical address: %010lx\n", __read_64bit_c0_register($26, 1)); #else @@ -98,7 +98,7 @@ static int __init swarm_setup(void) rtc_get_time = xicor_get_time; rtc_set_time = xicor_set_time; } - + if (m41t81_probe()) { printk("swarm setup: M41T81 RTC detected.\n"); rtc_get_time = m41t81_get_time; diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c index 62c760f14674..141a310d74d8 100644 --- a/arch/mips/sni/irq.c +++ b/arch/mips/sni/irq.c @@ -103,7 +103,7 @@ static unsigned int ls1bit8(unsigned int x) /* * hwint 1 deals with EISA and SCSI interrupts, - * + * * The EISA_INT bit in CSITPEND is high active, all others are low active. */ void pciasic_hwint1(struct pt_regs *regs) diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c index 8f67cee4317b..1b3f8a0903e1 100644 --- a/arch/mips/sni/setup.c +++ b/arch/mips/sni/setup.c @@ -111,7 +111,7 @@ static struct resource sni_mem_resource = { * The RM200/RM300 has a few holes in it's PCI/EISA memory address space used * for other purposes. Be paranoid and allocate all of the before the PCI * code gets a chance to to map anything else there ... - * + * * This leaves the following areas available: * * 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory diff --git a/arch/mips/tx4927/common/tx4927_irq_handler.S b/arch/mips/tx4927/common/tx4927_irq_handler.S index ca123e28d1ef..dd3ceda9d712 100644 --- a/arch/mips/tx4927/common/tx4927_irq_handler.S +++ b/arch/mips/tx4927/common/tx4927_irq_handler.S @@ -42,13 +42,13 @@ CLI .set at - mfc0 t0, CP0_CAUSE + mfc0 t0, CP0_CAUSE mfc0 t1, CP0_STATUS and t0, t1 - + andi t1, t0, STATUSF_IP7 /* cpu timer */ bnez t1, ll_ip7 - + /* IP6..IP3 multiplexed -- do not use */ andi t1, t0, STATUSF_IP2 /* tx4927 pic */ diff --git a/arch/mips/tx4927/common/tx4927_setup.c b/arch/mips/tx4927/common/tx4927_setup.c index 16bcbdc6d1cc..26d7c53612a8 100644 --- a/arch/mips/tx4927/common/tx4927_setup.c +++ b/arch/mips/tx4927/common/tx4927_setup.c @@ -152,7 +152,7 @@ dump_cp0(char *key) print_cp0(key, 16, "CONFIG ", read_c0_config()); return; } - + void print_pic(char *key, u32 reg, char *name) { printk("%s pic:0x%08x:%s=0x%08x\n", key, reg, name, diff --git a/arch/mips/tx4927/toshiba_rbtx4927/Makefile b/arch/mips/tx4927/toshiba_rbtx4927/Makefile index 86ca4cf2d587..c1a377a80a5d 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/Makefile +++ b/arch/mips/tx4927/toshiba_rbtx4927/Makefile @@ -1,5 +1,5 @@ -obj-y += toshiba_rbtx4927_prom.o -obj-y += toshiba_rbtx4927_setup.o -obj-y += toshiba_rbtx4927_irq.o +obj-y += toshiba_rbtx4927_prom.o +obj-y += toshiba_rbtx4927_setup.o +obj-y += toshiba_rbtx4927_irq.o EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c index fd5b433f83b7..aee07ff2212a 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c @@ -31,7 +31,7 @@ /* -IRQ Device +IRQ Device 00 RBTX4927-ISA/00 01 RBTX4927-ISA/01 PS2/Keyboard 02 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15) @@ -52,15 +52,15 @@ IRQ Device 16 TX4927-CP0/00 Software 0 17 TX4927-CP0/01 Software 1 18 TX4927-CP0/02 Cascade TX4927-CP0 -19 TX4927-CP0/03 Multiplexed -- do not use -20 TX4927-CP0/04 Multiplexed -- do not use -21 TX4927-CP0/05 Multiplexed -- do not use -22 TX4927-CP0/06 Multiplexed -- do not use +19 TX4927-CP0/03 Multiplexed -- do not use +20 TX4927-CP0/04 Multiplexed -- do not use +21 TX4927-CP0/05 Multiplexed -- do not use +22 TX4927-CP0/06 Multiplexed -- do not use 23 TX4927-CP0/07 CPU TIMER 24 TX4927-PIC/00 25 TX4927-PIC/01 -26 TX4927-PIC/02 +26 TX4927-PIC/02 27 TX4927-PIC/03 Cascade RBTX4927-IOC 28 TX4927-PIC/04 29 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet @@ -80,7 +80,7 @@ IRQ Device 43 TX4927-PIC/19 44 TX4927-PIC/20 45 TX4927-PIC/21 -46 TX4927-PIC/22 TX4927 PCI PCI-ERR +46 TX4927-PIC/22 TX4927 PCI PCI-ERR 47 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used) 48 TX4927-PIC/24 49 TX4927-PIC/25 @@ -100,7 +100,7 @@ IRQ Device 62 RBTX4927-IOC/06 63 RBTX4927-IOC/07 -NOTES: +NOTES: SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58 SouthBridge/ISA/pin=0 no pci irq used by this device SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14 @@ -175,19 +175,19 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB static const u32 toshiba_rbtx4927_irq_debug_flag = (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO | TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR -// | TOSHIBA_RBTX4927_IRQ_IOC_INIT -// | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP -// | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN -// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE -// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE -// | TOSHIBA_RBTX4927_IRQ_IOC_MASK -// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ -// | TOSHIBA_RBTX4927_IRQ_ISA_INIT -// | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP -// | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN -// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE -// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE -// | TOSHIBA_RBTX4927_IRQ_ISA_MASK +// | TOSHIBA_RBTX4927_IRQ_IOC_INIT +// | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP +// | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN +// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE +// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE +// | TOSHIBA_RBTX4927_IRQ_IOC_MASK +// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ +// | TOSHIBA_RBTX4927_IRQ_ISA_INIT +// | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP +// | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN +// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE +// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE +// | TOSHIBA_RBTX4927_IRQ_ISA_MASK // | TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ ); #endif diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c index 8724ea3ae04e..fc0720599fd9 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c @@ -395,7 +395,7 @@ static int __init tx4927_pcibios_init(void) /* enable secondary ide */ v08_43 |= 0x80; - /* + /* * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! * * This line of code is intended to provide the user with a work diff --git a/arch/mips/vr4181/common/Makefile b/arch/mips/vr4181/common/Makefile deleted file mode 100644 index f7587ca64ead..000000000000 --- a/arch/mips/vr4181/common/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Makefile for common code of NEC vr4181 based boards -# - -obj-y := irq.o int_handler.o serial.o time.o - -EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/vr4181/common/int_handler.S b/arch/mips/vr4181/common/int_handler.S deleted file mode 100644 index 2c041b8ee52b..000000000000 --- a/arch/mips/vr4181/common/int_handler.S +++ /dev/null @@ -1,206 +0,0 @@ -/* - * arch/mips/vr4181/common/int_handler.S - * - * Adapted to the VR4181 and almost entirely rewritten: - * Copyright (C) 1999 Bradley D. LaRonde and Michael Klar - * - * Clean up to conform to the new IRQ - * Copyright (C) 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - */ - -#include <asm/asm.h> -#include <asm/regdef.h> -#include <asm/mipsregs.h> -#include <asm/stackframe.h> - -#include <asm/vr4181/vr4181.h> - -/* - * [jsun] - * See include/asm/vr4181/irq.h for IRQ assignment and strategy. - */ - - .text - .set noreorder - - .align 5 - NESTED(vr4181_handle_irq, PT_SIZE, ra) - - .set noat - SAVE_ALL - CLI - - .set at - .set noreorder - - mfc0 t0, CP0_CAUSE - mfc0 t2, CP0_STATUS - - and t0, t2 - - /* we check IP3 first; it happens most frequently */ - andi t1, t0, STATUSF_IP3 - bnez t1, ll_cpu_ip3 - andi t1, t0, STATUSF_IP2 - bnez t1, ll_cpu_ip2 - andi t1, t0, STATUSF_IP7 /* cpu timer */ - bnez t1, ll_cputimer_irq - andi t1, t0, STATUSF_IP4 - bnez t1, ll_cpu_ip4 - andi t1, t0, STATUSF_IP5 - bnez t1, ll_cpu_ip5 - andi t1, t0, STATUSF_IP6 - bnez t1, ll_cpu_ip6 - andi t1, t0, STATUSF_IP0 /* software int 0 */ - bnez t1, ll_cpu_ip0 - andi t1, t0, STATUSF_IP1 /* software int 1 */ - bnez t1, ll_cpu_ip1 - nop - - .set reorder -do_spurious: - j spurious_interrupt - -/* - * regular CPU irqs - */ -ll_cputimer_irq: - li a0, VR4181_IRQ_TIMER - move a1, sp - jal do_IRQ - j ret_from_irq - - -ll_cpu_ip0: - li a0, VR4181_IRQ_SW1 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip1: - li a0, VR4181_IRQ_SW2 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip3: - li a0, VR4181_IRQ_INT1 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip4: - li a0, VR4181_IRQ_INT2 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip5: - li a0, VR4181_IRQ_INT3 - move a1, sp - jal do_IRQ - j ret_from_irq - -ll_cpu_ip6: - li a0, VR4181_IRQ_INT4 - move a1, sp - jal do_IRQ - j ret_from_irq - -/* - * One of the sys irq has happend. - * - * In the interest of speed, we first determine in the following order - * which 16-irq block have pending interrupts: - * sysint1 (16 sources, including cascading intrs from GPIO) - * sysint2 - * gpio (16 intr sources) - * - * Then we do binary search to find the exact interrupt source. - */ -ll_cpu_ip2: - - lui t3,%hi(VR4181_SYSINT1REG) - lhu t0,%lo(VR4181_SYSINT1REG)(t3) - lhu t2,%lo(VR4181_MSYSINT1REG)(t3) - and t0, 0xfffb /* hack - remove RTC Long 1 intr */ - and t0, t2 - beqz t0, check_sysint2 - - /* check for GPIO interrupts */ - andi t1, t0, 0x0100 - bnez t1, check_gpio_int - - /* so we have an interrupt in sysint1 which is not gpio int */ - li a0, VR4181_SYS_IRQ_BASE - 1 - j check_16 - -check_sysint2: - - lhu t0,%lo(VR4181_SYSINT2REG)(t3) - lhu t2,%lo(VR4181_MSYSINT2REG)(t3) - and t0, 0xfffe /* hack - remove RTC Long 2 intr */ - and t0, t2 - li a0, VR4181_SYS_IRQ_BASE + 16 - 1 - j check_16 - -check_gpio_int: - lui t3,%hi(VR4181_GPINTMSK) - lhu t0,%lo(VR4181_GPINTMSK)(t3) - lhu t2,%lo(VR4181_GPINTSTAT)(t3) - xori t0, 0xffff /* why? reverse logic? */ - and t0, t2 - li a0, VR4181_GPIO_IRQ_BASE - 1 - j check_16 - -/* - * When we reach check_16, we have 16-bit status in t0 and base irq number - * in a0. - */ -check_16: - andi t1, t0, 0xff - bnez t1, check_8 - - srl t0, 8 - addi a0, 8 - j check_8 - -/* - * When we reach check_8, we have 8-bit status in t0 and base irq number - * in a0. - */ -check_8: - andi t1, t0, 0xf - bnez t1, check_4 - - srl t0, 4 - addi a0, 4 - j check_4 - -/* - * When we reach check_4, we have 4-bit status in t0 and base irq number - * in a0. - */ -check_4: - andi t0, t0, 0xf - beqz t0, do_spurious - -loop: - andi t2, t0, 0x1 - srl t0, 1 - addi a0, 1 - beqz t2, loop - -found_it: - move a1, sp - jal do_IRQ - - j ret_from_irq - - END(vr4181_handle_irq) diff --git a/arch/mips/vr4181/common/irq.c b/arch/mips/vr4181/common/irq.c deleted file mode 100644 index 2cdf77c5cb3e..000000000000 --- a/arch/mips/vr4181/common/irq.c +++ /dev/null @@ -1,239 +0,0 @@ -/* - * Copyright (C) 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) - * - * linux/arch/mips/vr4181/common/irq.c - * Completely re-written to use the new irq.c - * - * Credits to Bradley D. LaRonde and Michael Klar for writing the original - * irq.c file which was derived from the common irq.c file. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include <linux/types.h> -#include <linux/init.h> -#include <linux/kernel_stat.h> -#include <linux/signal.h> -#include <linux/sched.h> -#include <linux/interrupt.h> -#include <linux/slab.h> -#include <linux/random.h> - -#include <asm/irq.h> -#include <asm/mipsregs.h> -#include <asm/gdb-stub.h> - -#include <asm/vr4181/vr4181.h> - -/* - * Strategy: - * - * We essentially have three irq controllers, CPU, system, and gpio. - * - * CPU irq controller is taken care by arch/mips/kernel/irq_cpu.c and - * CONFIG_IRQ_CPU config option. - * - * We here provide sys_irq and gpio_irq controller code. - */ - -static int sys_irq_base; -static int gpio_irq_base; - -/* ---------------------- sys irq ------------------------ */ -static void -sys_irq_enable(unsigned int irq) -{ - irq -= sys_irq_base; - if (irq < 16) { - *VR4181_MSYSINT1REG |= (u16)(1 << irq); - } else { - irq -= 16; - *VR4181_MSYSINT2REG |= (u16)(1 << irq); - } -} - -static void -sys_irq_disable(unsigned int irq) -{ - irq -= sys_irq_base; - if (irq < 16) { - *VR4181_MSYSINT1REG &= ~((u16)(1 << irq)); - } else { - irq -= 16; - *VR4181_MSYSINT2REG &= ~((u16)(1 << irq)); - } - -} - -static unsigned int -sys_irq_startup(unsigned int irq) -{ - sys_irq_enable(irq); - return 0; -} - -#define sys_irq_shutdown sys_irq_disable -#define sys_irq_ack sys_irq_disable - -static void -sys_irq_end(unsigned int irq) -{ - if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - sys_irq_enable(irq); -} - -static hw_irq_controller sys_irq_controller = { - "vr4181_sys_irq", - sys_irq_startup, - sys_irq_shutdown, - sys_irq_enable, - sys_irq_disable, - sys_irq_ack, - sys_irq_end, - NULL /* no affinity stuff for UP */ -}; - -/* ---------------------- gpio irq ------------------------ */ -/* gpio irq lines use reverse logic */ -static void -gpio_irq_enable(unsigned int irq) -{ - irq -= gpio_irq_base; - *VR4181_GPINTMSK &= ~((u16)(1 << irq)); -} - -static void -gpio_irq_disable(unsigned int irq) -{ - irq -= gpio_irq_base; - *VR4181_GPINTMSK |= (u16)(1 << irq); -} - -static unsigned int -gpio_irq_startup(unsigned int irq) -{ - gpio_irq_enable(irq); - - irq -= gpio_irq_base; - *VR4181_GPINTEN |= (u16)(1 << irq ); - - return 0; -} - -static void -gpio_irq_shutdown(unsigned int irq) -{ - gpio_irq_disable(irq); - - irq -= gpio_irq_base; - *VR4181_GPINTEN &= ~((u16)(1 << irq )); -} - -static void -gpio_irq_ack(unsigned int irq) -{ - u16 irqtype; - u16 irqshift; - - gpio_irq_disable(irq); - - /* we clear interrupt if it is edge triggered */ - irq -= gpio_irq_base; - if (irq < 8) { - irqtype = *VR4181_GPINTTYPL; - irqshift = 2 << (irq*2); - } else { - irqtype = *VR4181_GPINTTYPH; - irqshift = 2 << ((irq-8)*2); - } - if ( ! (irqtype & irqshift) ) { - *VR4181_GPINTSTAT = (u16) (1 << irq); - } -} - -static void -gpio_irq_end(unsigned int irq) -{ - if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - gpio_irq_enable(irq); -} - -static hw_irq_controller gpio_irq_controller = { - "vr4181_gpio_irq", - gpio_irq_startup, - gpio_irq_shutdown, - gpio_irq_enable, - gpio_irq_disable, - gpio_irq_ack, - gpio_irq_end, - NULL /* no affinity stuff for UP */ -}; - -/* --------------------- IRQ init stuff ---------------------- */ - -extern asmlinkage void vr4181_handle_irq(void); -extern void breakpoint(void); -extern int setup_irq(unsigned int irq, struct irqaction *irqaction); -extern void mips_cpu_irq_init(u32 irq_base); - -static struct irqaction cascade = - { no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade", NULL, NULL }; -static struct irqaction reserved = - { no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade", NULL, NULL }; - -void __init arch_init_irq(void) -{ - int i; - - set_except_vector(0, vr4181_handle_irq); - - /* init CPU irqs */ - mips_cpu_irq_init(VR4181_CPU_IRQ_BASE); - - /* init sys irqs */ - sys_irq_base = VR4181_SYS_IRQ_BASE; - for (i=sys_irq_base; i < sys_irq_base + VR4181_NUM_SYS_IRQ; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 1; - irq_desc[i].handler = &sys_irq_controller; - } - - /* init gpio irqs */ - gpio_irq_base = VR4181_GPIO_IRQ_BASE; - for (i=gpio_irq_base; i < gpio_irq_base + VR4181_NUM_GPIO_IRQ; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 1; - irq_desc[i].handler = &gpio_irq_controller; - } - - /* Default all ICU IRQs to off ... */ - *VR4181_MSYSINT1REG = 0; - *VR4181_MSYSINT2REG = 0; - - /* We initialize the level 2 ICU registers to all bits disabled. */ - *VR4181_MPIUINTREG = 0; - *VR4181_MAIUINTREG = 0; - *VR4181_MKIUINTREG = 0; - - /* disable all GPIO intrs */ - *VR4181_GPINTMSK = 0xffff; - - /* vector handler. What these do is register the IRQ as non-sharable */ - setup_irq(VR4181_IRQ_INT0, &cascade); - setup_irq(VR4181_IRQ_GIU, &cascade); - - /* - * RTC interrupts are interesting. They have two destinations. - * One is at sys irq controller, and the other is at CPU IP3 and IP4. - * RTC timer is used as system timer. - * We enable them here, but timer routine will register later - * with CPU IP3/IP4. - */ - setup_irq(VR4181_IRQ_RTCL1, &reserved); - setup_irq(VR4181_IRQ_RTCL2, &reserved); -} diff --git a/arch/mips/vr4181/common/serial.c b/arch/mips/vr4181/common/serial.c deleted file mode 100644 index 3f62c62b107f..000000000000 --- a/arch/mips/vr4181/common/serial.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * arch/mips/vr4181/common/serial.c - * initialize serial port on vr4181. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -/* - * [jsun, 010925] - * You need to make sure rs_table has at least one element in - * drivers/char/serial.c file. There is no good way to do it right - * now. A workaround is to include CONFIG_SERIAL_MANY_PORTS in your - * configure file, which would gives you 64 ports and wastes 11K ram. - */ - -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/serial.h> - -#include <asm/vr4181/vr4181.h> - -void __init vr4181_init_serial(void) -{ - struct serial_struct s; - - /* turn on UART clock */ - *VR4181_CMUCLKMSK |= VR4181_CMUCLKMSK_MSKSIU; - - /* clear memory */ - memset(&s, 0, sizeof(s)); - - s.line = 0; /* we set the first one */ - s.baud_base = 1152000; - s.irq = VR4181_IRQ_SIU; - s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; /* STD_COM_FLAGS */ - s.iomem_base = (u8*)VR4181_SIURB; - s.iomem_reg_shift = 0; - s.io_type = SERIAL_IO_MEM; - if (early_serial_setup(&s) != 0) { - panic("vr4181_init_serial() failed!"); - } -} - diff --git a/arch/mips/vr4181/common/time.c b/arch/mips/vr4181/common/time.c deleted file mode 100644 index 17814076b6f4..000000000000 --- a/arch/mips/vr4181/common/time.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * rtc and time ops for vr4181. Part of code is drived from - * linux-vr, originally written by Bradley D. LaRonde & Michael Klar. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include <linux/kernel.h> -#include <linux/spinlock.h> -#include <linux/param.h> /* for HZ */ -#include <linux/time.h> -#include <linux/interrupt.h> - -#include <asm/system.h> -#include <asm/time.h> - -#include <asm/vr4181/vr4181.h> - -#define COUNTS_PER_JIFFY ((32768 + HZ/2) / HZ) - -/* - * RTC ops - */ - -DEFINE_SPINLOCK(rtc_lock); - -/* per VR41xx docs, bad data can be read if between 2 counts */ -static inline unsigned short -read_time_reg(volatile unsigned short *reg) -{ - unsigned short value; - do { - value = *reg; - barrier(); - } while (value != *reg); - return value; -} - -static unsigned long -vr4181_rtc_get_time(void) -{ - unsigned short regh, regm, regl; - - // why this crazy order, you ask? to guarantee that neither m - // nor l wrap before all 3 read - do { - regm = read_time_reg(VR4181_ETIMEMREG); - barrier(); - regh = read_time_reg(VR4181_ETIMEHREG); - barrier(); - regl = read_time_reg(VR4181_ETIMELREG); - } while (regm != read_time_reg(VR4181_ETIMEMREG)); - return ((regh << 17) | (regm << 1) | (regl >> 15)); -} - -static int -vr4181_rtc_set_time(unsigned long timeval) -{ - unsigned short intreg; - unsigned long flags; - - spin_lock_irqsave(&rtc_lock, flags); - intreg = *VR4181_RTCINTREG & 0x05; - barrier(); - *VR4181_ETIMELREG = timeval << 15; - *VR4181_ETIMEMREG = timeval >> 1; - *VR4181_ETIMEHREG = timeval >> 17; - barrier(); - // assume that any ints that just triggered are invalid, since the - // time value is written non-atomically in 3 separate regs - *VR4181_RTCINTREG = 0x05 ^ intreg; - spin_unlock_irqrestore(&rtc_lock, flags); - - return 0; -} - - -/* - * timer interrupt routine (wrapper) - * - * we need our own interrupt routine because we need to clear - * RTC1 interrupt. - */ -static void -vr4181_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) -{ - /* Clear the interrupt. */ - *VR4181_RTCINTREG = 0x2; - - /* call the generic one */ - timer_interrupt(irq, dev_id, regs); -} - - -/* - * vr4181_time_init: - * - * We pick the following choices: - * . we use elapsed timer as the RTC. We set some reasonable init data since - * it does not persist across reset - * . we use RTC1 as the system timer interrupt source. - * . we use CPU counter for fast_gettimeoffset and we calivrate the cpu - * frequency. In other words, we use calibrate_div64_gettimeoffset(). - * . we use our own timer interrupt routine which clears the interrupt - * and then calls the generic high-level timer interrupt routine. - * - */ - -extern int setup_irq(unsigned int irq, struct irqaction *irqaction); - -static void -vr4181_timer_setup(struct irqaction *irq) -{ - /* over-write the handler to be our own one */ - irq->handler = vr4181_timer_interrupt; - - /* sets up the frequency */ - *VR4181_RTCL1LREG = COUNTS_PER_JIFFY; - *VR4181_RTCL1HREG = 0; - - /* and ack any pending ints */ - *VR4181_RTCINTREG = 0x2; - - /* setup irqaction */ - setup_irq(VR4181_IRQ_INT1, irq); - -} - -void -vr4181_init_time(void) -{ - /* setup hookup functions */ - rtc_get_time = vr4181_rtc_get_time; - rtc_set_time = vr4181_rtc_set_time; - - board_timer_setup = vr4181_timer_setup; -} - diff --git a/arch/mips/vr4181/osprey/Makefile b/arch/mips/vr4181/osprey/Makefile deleted file mode 100644 index 34be05790883..000000000000 --- a/arch/mips/vr4181/osprey/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Makefile for common code of NEC Osprey board -# - -obj-y := setup.o prom.o reset.o - -obj-$(CONFIG_KGDB) += dbg_io.o diff --git a/arch/mips/vr4181/osprey/dbg_io.c b/arch/mips/vr4181/osprey/dbg_io.c deleted file mode 100644 index 5e8a84072d5b..000000000000 --- a/arch/mips/vr4181/osprey/dbg_io.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * kgdb io functions for osprey. We use the serial port on debug board. - * - * Copyright (C) 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -/* ======================= CONFIG ======================== */ - -/* [jsun] we use the second serial port for kdb */ -#define BASE 0xb7fffff0 -#define MAX_BAUD 115200 - -/* distance in bytes between two serial registers */ -#define REG_OFFSET 1 - -/* - * 0 - kgdb does serial init - * 1 - kgdb skip serial init - */ -static int remoteDebugInitialized = 1; - -/* - * the default baud rate *if* kgdb does serial init - */ -#define BAUD_DEFAULT UART16550_BAUD_38400 - -/* ======================= END OF CONFIG ======================== */ - -typedef unsigned char uint8; -typedef unsigned int uint32; - -#define UART16550_BAUD_2400 2400 -#define UART16550_BAUD_4800 4800 -#define UART16550_BAUD_9600 9600 -#define UART16550_BAUD_19200 19200 -#define UART16550_BAUD_38400 38400 -#define UART16550_BAUD_57600 57600 -#define UART16550_BAUD_115200 115200 - -#define UART16550_PARITY_NONE 0 -#define UART16550_PARITY_ODD 0x08 -#define UART16550_PARITY_EVEN 0x18 -#define UART16550_PARITY_MARK 0x28 -#define UART16550_PARITY_SPACE 0x38 - -#define UART16550_DATA_5BIT 0x0 -#define UART16550_DATA_6BIT 0x1 -#define UART16550_DATA_7BIT 0x2 -#define UART16550_DATA_8BIT 0x3 - -#define UART16550_STOP_1BIT 0x0 -#define UART16550_STOP_2BIT 0x4 - -/* register offset */ -#define OFS_RCV_BUFFER 0 -#define OFS_TRANS_HOLD 0 -#define OFS_SEND_BUFFER 0 -#define OFS_INTR_ENABLE (1*REG_OFFSET) -#define OFS_INTR_ID (2*REG_OFFSET) -#define OFS_DATA_FORMAT (3*REG_OFFSET) -#define OFS_LINE_CONTROL (3*REG_OFFSET) -#define OFS_MODEM_CONTROL (4*REG_OFFSET) -#define OFS_RS232_OUTPUT (4*REG_OFFSET) -#define OFS_LINE_STATUS (5*REG_OFFSET) -#define OFS_MODEM_STATUS (6*REG_OFFSET) -#define OFS_RS232_INPUT (6*REG_OFFSET) -#define OFS_SCRATCH_PAD (7*REG_OFFSET) - -#define OFS_DIVISOR_LSB (0*REG_OFFSET) -#define OFS_DIVISOR_MSB (1*REG_OFFSET) - - -/* memory-mapped read/write of the port */ -#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) -#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) - -void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) -{ - /* disable interrupts */ - UART16550_WRITE(OFS_INTR_ENABLE, 0); - - /* set up buad rate */ - { - uint32 divisor; - - /* set DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - - /* set divisor */ - divisor = MAX_BAUD / baud; - UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); - UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); - - /* clear DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x0); - } - - /* set data format */ - UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); -} - - -uint8 getDebugChar(void) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(BAUD_DEFAULT, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); - return UART16550_READ(OFS_RCV_BUFFER); -} - - -int putDebugChar(uint8 byte) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(BAUD_DEFAULT, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); - UART16550_WRITE(OFS_SEND_BUFFER, byte); - return 1; -} diff --git a/arch/mips/vr4181/osprey/prom.c b/arch/mips/vr4181/osprey/prom.c deleted file mode 100644 index af0d14561619..000000000000 --- a/arch/mips/vr4181/osprey/prom.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * arch/mips/vr4181/osprey/prom.c - * prom code for osprey. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/mm.h> -#include <linux/bootmem.h> -#include <asm/bootinfo.h> -#include <asm/addrspace.h> - -const char *get_system_type(void) -{ - return "NEC_Vr41xx Osprey"; -} - -/* - * [jsun] right now we assume it is the nec debug monitor, which does - * not pass any arguments. - */ -void __init prom_init(void) -{ - // cmdline is now set in default config - // strcpy(arcs_cmdline, "ip=bootp "); - // strcat(arcs_cmdline, "ether=46,0x03fe0300,eth0 "); - // strcpy(arcs_cmdline, "ether=0,0x0300,eth0 " - // strcat(arcs_cmdline, "video=vr4181fb:xres:240,yres:320,bpp:8 "); - - mips_machgroup = MACH_GROUP_NEC_VR41XX; - mips_machtype = MACH_NEC_OSPREY; - - /* 16MB fixed */ - add_memory_region(0, 16 << 20, BOOT_MEM_RAM); -} - -unsigned long __init prom_free_prom_memory(void) -{ - return 0; -} diff --git a/arch/mips/vr4181/osprey/reset.c b/arch/mips/vr4181/osprey/reset.c deleted file mode 100644 index 036ae83d89d6..000000000000 --- a/arch/mips/vr4181/osprey/reset.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 1997, 2001 Ralf Baechle - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - */ -#include <linux/sched.h> -#include <linux/mm.h> -#include <asm/io.h> -#include <asm/cacheflush.h> -#include <asm/processor.h> -#include <asm/reboot.h> -#include <asm/system.h> - -void nec_osprey_restart(char *command) -{ - set_c0_status(ST0_ERL); - change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); - flush_cache_all(); - write_c0_wired(0); - __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); -} - -void nec_osprey_halt(void) -{ - printk(KERN_NOTICE "\n** You can safely turn off the power\n"); - while (1) - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); -} - -void nec_osprey_power_off(void) -{ - nec_osprey_halt(); -} diff --git a/arch/mips/vr4181/osprey/setup.c b/arch/mips/vr4181/osprey/setup.c deleted file mode 100644 index 2ff7140e7ed7..000000000000 --- a/arch/mips/vr4181/osprey/setup.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * linux/arch/mips/vr4181/setup.c - * - * VR41xx setup routines - * - * Copyright (C) 1999 Bradley D. LaRonde - * Copyright (C) 1999, 2000 Michael Klar - * - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - */ - -#include <linux/ide.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <asm/reboot.h> -#include <asm/vr4181/vr4181.h> -#include <asm/io.h> - - -extern void nec_osprey_restart(char* c); -extern void nec_osprey_halt(void); -extern void nec_osprey_power_off(void); - -extern void vr4181_init_serial(void); -extern void vr4181_init_time(void); - -static void __init nec_osprey_setup(void) -{ - set_io_port_base(VR4181_PORT_BASE); - isa_slot_offset = VR4181_ISAMEM_BASE; - - vr4181_init_serial(); - vr4181_init_time(); - - _machine_restart = nec_osprey_restart; - _machine_halt = nec_osprey_halt; - _machine_power_off = nec_osprey_power_off; - - /* setup resource limit */ - ioport_resource.end = 0xffffffff; - iomem_resource.end = 0xffffffff; - - /* [jsun] hack */ - /* - printk("[jsun] hack to change external ISA control register, %x -> %x\n", - (*VR4181_XISACTL), - (*VR4181_XISACTL) | 0x2); - *VR4181_XISACTL |= 0x2; - */ - - // *VR4181_GPHIBSTH = 0x2000; - // *VR4181_GPMD0REG = 0x00c0; - // *VR4181_GPINTEN = 1<<6; - - /* [jsun] I believe this will get the interrupt type right - * for the ether port. - */ - *VR4181_GPINTTYPL = 0x3000; -} - -early_initcall(nec_osprey_setup); diff --git a/arch/mips/vr41xx/casio-e55/setup.c b/arch/mips/vr41xx/casio-e55/setup.c index aa8605ab76ff..d29201acc4f3 100644 --- a/arch/mips/vr41xx/casio-e55/setup.c +++ b/arch/mips/vr41xx/casio-e55/setup.c @@ -23,11 +23,6 @@ #include <asm/io.h> #include <asm/vr41xx/e55.h> -const char *get_system_type(void) -{ - return "CASIO CASSIOPEIA E-11/15/55/65"; -} - static int __init casio_e55_setup(void) { set_io_port_base(IO_PORT_BASE); diff --git a/arch/mips/vr41xx/common/Makefile b/arch/mips/vr41xx/common/Makefile index fa98ef3855bc..9096302a7ecc 100644 --- a/arch/mips/vr41xx/common/Makefile +++ b/arch/mips/vr41xx/common/Makefile @@ -2,7 +2,7 @@ # Makefile for common code of the NEC VR4100 series. # -obj-y += bcu.o cmu.o icu.o init.o int-handler.o pmu.o +obj-y += bcu.o cmu.o icu.o init.o int-handler.o irq.o pmu.o type.o obj-$(CONFIG_VRC4173) += vrc4173.o EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c index c842661144cb..0b73c5ab3c0c 100644 --- a/arch/mips/vr41xx/common/icu.c +++ b/arch/mips/vr41xx/common/icu.c @@ -3,8 +3,7 @@ * * Copyright (C) 2001-2002 MontaVista Software Inc. * Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com> - * Copyright (C) 2003-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> - * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2003-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -31,7 +30,7 @@ */ #include <linux/errno.h> #include <linux/init.h> -#include <linux/interrupt.h> +#include <linux/ioport.h> #include <linux/irq.h> #include <linux/module.h> #include <linux/smp.h> @@ -39,34 +38,24 @@ #include <asm/cpu.h> #include <asm/io.h> -#include <asm/irq.h> -#include <asm/irq_cpu.h> #include <asm/vr41xx/vr41xx.h> -extern asmlinkage void vr41xx_handle_interrupt(void); - -extern void init_vr41xx_giuint_irq(void); -extern void giuint_irq_dispatch(struct pt_regs *regs); - -static uint32_t icu1_base; -static uint32_t icu2_base; - -static struct irqaction icu_cascade = { - .handler = no_action, - .mask = CPU_MASK_NONE, - .name = "cascade", -}; +static void __iomem *icu1_base; +static void __iomem *icu2_base; static unsigned char sysint1_assign[16] = { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; static unsigned char sysint2_assign[16] = { - 2, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; + 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; -#define SYSINT1REG_TYPE1 KSEG1ADDR(0x0b000080) -#define SYSINT2REG_TYPE1 KSEG1ADDR(0x0b000200) +#define ICU1_TYPE1_BASE 0x0b000080UL +#define ICU2_TYPE1_BASE 0x0b000200UL -#define SYSINT1REG_TYPE2 KSEG1ADDR(0x0f000080) -#define SYSINT2REG_TYPE2 KSEG1ADDR(0x0f0000a0) +#define ICU1_TYPE2_BASE 0x0f000080UL +#define ICU2_TYPE2_BASE 0x0f0000a0UL + +#define ICU1_SIZE 0x20 +#define ICU2_SIZE 0x1c #define SYSINT1REG 0x00 #define PIUINTREG 0x02 @@ -106,61 +95,61 @@ static unsigned char sysint2_assign[16] = { #define SYSINT1_IRQ_TO_PIN(x) ((x) - SYSINT1_IRQ_BASE) /* Pin 0-15 */ #define SYSINT2_IRQ_TO_PIN(x) ((x) - SYSINT2_IRQ_BASE) /* Pin 0-15 */ -#define read_icu1(offset) readw(icu1_base + (offset)) -#define write_icu1(val, offset) writew((val), icu1_base + (offset)) +#define INT_TO_IRQ(x) ((x) + 2) /* Int0-4 -> IRQ2-6 */ + +#define icu1_read(offset) readw(icu1_base + (offset)) +#define icu1_write(offset, value) writew((value), icu1_base + (offset)) -#define read_icu2(offset) readw(icu2_base + (offset)) -#define write_icu2(val, offset) writew((val), icu2_base + (offset)) +#define icu2_read(offset) readw(icu2_base + (offset)) +#define icu2_write(offset, value) writew((value), icu2_base + (offset)) #define INTASSIGN_MAX 4 #define INTASSIGN_MASK 0x0007 -static inline uint16_t set_icu1(uint8_t offset, uint16_t set) +static inline uint16_t icu1_set(uint8_t offset, uint16_t set) { - uint16_t res; + uint16_t data; - res = read_icu1(offset); - res |= set; - write_icu1(res, offset); + data = icu1_read(offset); + data |= set; + icu1_write(offset, data); - return res; + return data; } -static inline uint16_t clear_icu1(uint8_t offset, uint16_t clear) +static inline uint16_t icu1_clear(uint8_t offset, uint16_t clear) { - uint16_t res; + uint16_t data; - res = read_icu1(offset); - res &= ~clear; - write_icu1(res, offset); + data = icu1_read(offset); + data &= ~clear; + icu1_write(offset, data); - return res; + return data; } -static inline uint16_t set_icu2(uint8_t offset, uint16_t set) +static inline uint16_t icu2_set(uint8_t offset, uint16_t set) { - uint16_t res; + uint16_t data; - res = read_icu2(offset); - res |= set; - write_icu2(res, offset); + data = icu2_read(offset); + data |= set; + icu2_write(offset, data); - return res; + return data; } -static inline uint16_t clear_icu2(uint8_t offset, uint16_t clear) +static inline uint16_t icu2_clear(uint8_t offset, uint16_t clear) { - uint16_t res; + uint16_t data; - res = read_icu2(offset); - res &= ~clear; - write_icu2(res, offset); + data = icu2_read(offset); + data &= ~clear; + icu2_write(offset, data); - return res; + return data; } -/*=======================================================================*/ - void vr41xx_enable_piuint(uint16_t mask) { irq_desc_t *desc = irq_desc + PIU_IRQ; @@ -169,7 +158,7 @@ void vr41xx_enable_piuint(uint16_t mask) if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - set_icu1(MPIUINTREG, mask); + icu1_set(MPIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -184,7 +173,7 @@ void vr41xx_disable_piuint(uint16_t mask) if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - clear_icu1(MPIUINTREG, mask); + icu1_clear(MPIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -199,7 +188,7 @@ void vr41xx_enable_aiuint(uint16_t mask) if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - set_icu1(MAIUINTREG, mask); + icu1_set(MAIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -214,7 +203,7 @@ void vr41xx_disable_aiuint(uint16_t mask) if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - clear_icu1(MAIUINTREG, mask); + icu1_clear(MAIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -229,7 +218,7 @@ void vr41xx_enable_kiuint(uint16_t mask) if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - set_icu1(MKIUINTREG, mask); + icu1_set(MKIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -244,7 +233,7 @@ void vr41xx_disable_kiuint(uint16_t mask) if (current_cpu_data.cputype == CPU_VR4111 || current_cpu_data.cputype == CPU_VR4121) { spin_lock_irqsave(&desc->lock, flags); - clear_icu1(MKIUINTREG, mask); + icu1_clear(MKIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -257,7 +246,7 @@ void vr41xx_enable_dsiuint(uint16_t mask) unsigned long flags; spin_lock_irqsave(&desc->lock, flags); - set_icu1(MDSIUINTREG, mask); + icu1_set(MDSIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } @@ -269,7 +258,7 @@ void vr41xx_disable_dsiuint(uint16_t mask) unsigned long flags; spin_lock_irqsave(&desc->lock, flags); - clear_icu1(MDSIUINTREG, mask); + icu1_clear(MDSIUINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } @@ -281,7 +270,7 @@ void vr41xx_enable_firint(uint16_t mask) unsigned long flags; spin_lock_irqsave(&desc->lock, flags); - set_icu2(MFIRINTREG, mask); + icu2_set(MFIRINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } @@ -293,7 +282,7 @@ void vr41xx_disable_firint(uint16_t mask) unsigned long flags; spin_lock_irqsave(&desc->lock, flags); - clear_icu2(MFIRINTREG, mask); + icu2_clear(MFIRINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } @@ -308,7 +297,7 @@ void vr41xx_enable_pciint(void) current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(PCIINT0, MPCIINTREG); + icu2_write(MPCIINTREG, PCIINT0); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -324,7 +313,7 @@ void vr41xx_disable_pciint(void) current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(0, MPCIINTREG); + icu2_write(MPCIINTREG, 0); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -340,7 +329,7 @@ void vr41xx_enable_scuint(void) current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(SCUINT0, MSCUINTREG); + icu2_write(MSCUINTREG, SCUINT0); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -356,7 +345,7 @@ void vr41xx_disable_scuint(void) current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(0, MSCUINTREG); + icu2_write(MSCUINTREG, 0); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -372,7 +361,7 @@ void vr41xx_enable_csiint(uint16_t mask) current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - set_icu2(MCSIINTREG, mask); + icu2_set(MCSIINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -388,7 +377,7 @@ void vr41xx_disable_csiint(uint16_t mask) current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - clear_icu2(MCSIINTREG, mask); + icu2_clear(MCSIINTREG, mask); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -404,7 +393,7 @@ void vr41xx_enable_bcuint(void) current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(BCUINTR, MBCUINTREG); + icu2_write(MBCUINTREG, BCUINTR); spin_unlock_irqrestore(&desc->lock, flags); } } @@ -420,30 +409,28 @@ void vr41xx_disable_bcuint(void) current_cpu_data.cputype == CPU_VR4131 || current_cpu_data.cputype == CPU_VR4133) { spin_lock_irqsave(&desc->lock, flags); - write_icu2(0, MBCUINTREG); + icu2_write(MBCUINTREG, 0); spin_unlock_irqrestore(&desc->lock, flags); } } EXPORT_SYMBOL(vr41xx_disable_bcuint); -/*=======================================================================*/ - static unsigned int startup_sysint1_irq(unsigned int irq) { - set_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq)); + icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); return 0; /* never anything pending */ } static void shutdown_sysint1_irq(unsigned int irq) { - clear_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq)); + icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); } static void enable_sysint1_irq(unsigned int irq) { - set_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq)); + icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); } #define disable_sysint1_irq shutdown_sysint1_irq @@ -452,7 +439,7 @@ static void enable_sysint1_irq(unsigned int irq) static void end_sysint1_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - set_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq)); + icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); } static struct hw_interrupt_type sysint1_irq_type = { @@ -465,23 +452,21 @@ static struct hw_interrupt_type sysint1_irq_type = { .end = end_sysint1_irq, }; -/*=======================================================================*/ - static unsigned int startup_sysint2_irq(unsigned int irq) { - set_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq)); + icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); return 0; /* never anything pending */ } static void shutdown_sysint2_irq(unsigned int irq) { - clear_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq)); + icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); } static void enable_sysint2_irq(unsigned int irq) { - set_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq)); + icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); } #define disable_sysint2_irq shutdown_sysint2_irq @@ -490,7 +475,7 @@ static void enable_sysint2_irq(unsigned int irq) static void end_sysint2_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - set_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq)); + icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); } static struct hw_interrupt_type sysint2_irq_type = { @@ -503,8 +488,6 @@ static struct hw_interrupt_type sysint2_irq_type = { .end = end_sysint2_irq, }; -/*=======================================================================*/ - static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) { irq_desc_t *desc = irq_desc + irq; @@ -515,8 +498,8 @@ static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) spin_lock_irq(&desc->lock); - intassign0 = read_icu1(INTASSIGN0); - intassign1 = read_icu1(INTASSIGN1); + intassign0 = icu1_read(INTASSIGN0); + intassign1 = icu1_read(INTASSIGN1); switch (pin) { case 0: @@ -556,8 +539,8 @@ static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) } sysint1_assign[pin] = assign; - write_icu1(intassign0, INTASSIGN0); - write_icu1(intassign1, INTASSIGN1); + icu1_write(INTASSIGN0, intassign0); + icu1_write(INTASSIGN1, intassign1); spin_unlock_irq(&desc->lock); @@ -574,8 +557,8 @@ static inline int set_sysint2_assign(unsigned int irq, unsigned char assign) spin_lock_irq(&desc->lock); - intassign2 = read_icu1(INTASSIGN2); - intassign3 = read_icu1(INTASSIGN3); + intassign2 = icu1_read(INTASSIGN2); + intassign3 = icu1_read(INTASSIGN3); switch (pin) { case 0: @@ -623,8 +606,8 @@ static inline int set_sysint2_assign(unsigned int irq, unsigned char assign) } sysint2_assign[pin] = assign; - write_icu1(intassign2, INTASSIGN2); - write_icu1(intassign3, INTASSIGN3); + icu1_write(INTASSIGN2, intassign2); + icu1_write(INTASSIGN3, intassign3); spin_unlock_irq(&desc->lock); @@ -651,88 +634,92 @@ int vr41xx_set_intassign(unsigned int irq, unsigned char intassign) EXPORT_SYMBOL(vr41xx_set_intassign); -/*=======================================================================*/ - -asmlinkage void irq_dispatch(unsigned char intnum, struct pt_regs *regs) +static int icu_get_irq(unsigned int irq, struct pt_regs *regs) { uint16_t pend1, pend2; uint16_t mask1, mask2; int i; - pend1 = read_icu1(SYSINT1REG); - mask1 = read_icu1(MSYSINT1REG); + pend1 = icu1_read(SYSINT1REG); + mask1 = icu1_read(MSYSINT1REG); - pend2 = read_icu2(SYSINT2REG); - mask2 = read_icu2(MSYSINT2REG); + pend2 = icu2_read(SYSINT2REG); + mask2 = icu2_read(MSYSINT2REG); mask1 &= pend1; mask2 &= pend2; if (mask1) { for (i = 0; i < 16; i++) { - if (intnum == sysint1_assign[i] && - (mask1 & ((uint16_t)1 << i))) { - if (i == 8) - giuint_irq_dispatch(regs); - else - do_IRQ(SYSINT1_IRQ(i), regs); - return; - } + if (irq == INT_TO_IRQ(sysint1_assign[i]) && (mask1 & (1 << i))) + return SYSINT1_IRQ(i); } } if (mask2) { for (i = 0; i < 16; i++) { - if (intnum == sysint2_assign[i] && - (mask2 & ((uint16_t)1 << i))) { - do_IRQ(SYSINT2_IRQ(i), regs); - return; - } + if (irq == INT_TO_IRQ(sysint2_assign[i]) && (mask2 & (1 << i))) + return SYSINT2_IRQ(i); } } printk(KERN_ERR "spurious ICU interrupt: %04x,%04x\n", pend1, pend2); atomic_inc(&irq_err_count); -} -/*=======================================================================*/ + return -1; +} static int __init vr41xx_icu_init(void) { + unsigned long icu1_start, icu2_start; + int i; + switch (current_cpu_data.cputype) { case CPU_VR4111: case CPU_VR4121: - icu1_base = SYSINT1REG_TYPE1; - icu2_base = SYSINT2REG_TYPE1; + icu1_start = ICU1_TYPE1_BASE; + icu2_start = ICU2_TYPE1_BASE; break; case CPU_VR4122: case CPU_VR4131: case CPU_VR4133: - icu1_base = SYSINT1REG_TYPE2; - icu2_base = SYSINT2REG_TYPE2; + icu1_start = ICU1_TYPE2_BASE; + icu2_start = ICU2_TYPE2_BASE; break; default: printk(KERN_ERR "ICU: Unexpected CPU of NEC VR4100 series\n"); - return -EINVAL; + return -ENODEV; } - write_icu1(0, MSYSINT1REG); - write_icu1(0xffff, MGIUINTLREG); + if (request_mem_region(icu1_start, ICU1_SIZE, "ICU") == NULL) + return -EBUSY; - write_icu2(0, MSYSINT2REG); - write_icu2(0xffff, MGIUINTHREG); + if (request_mem_region(icu2_start, ICU2_SIZE, "ICU") == NULL) { + release_mem_region(icu1_start, ICU1_SIZE); + return -EBUSY; + } - return 0; -} + icu1_base = ioremap(icu1_start, ICU1_SIZE); + if (icu1_base == NULL) { + release_mem_region(icu1_start, ICU1_SIZE); + release_mem_region(icu2_start, ICU2_SIZE); + return -ENOMEM; + } -early_initcall(vr41xx_icu_init); + icu2_base = ioremap(icu2_start, ICU2_SIZE); + if (icu2_base == NULL) { + iounmap(icu1_base); + release_mem_region(icu1_start, ICU1_SIZE); + release_mem_region(icu2_start, ICU2_SIZE); + return -ENOMEM; + } -/*=======================================================================*/ + icu1_write(MSYSINT1REG, 0); + icu1_write(MGIUINTLREG, 0xffff); -static inline void init_vr41xx_icu_irq(void) -{ - int i; + icu2_write(MSYSINT2REG, 0); + icu2_write(MGIUINTHREG, 0xffff); for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) irq_desc[i].handler = &sysint1_irq_type; @@ -740,18 +727,13 @@ static inline void init_vr41xx_icu_irq(void) for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) irq_desc[i].handler = &sysint2_irq_type; - setup_irq(INT0_CASCADE_IRQ, &icu_cascade); - setup_irq(INT1_CASCADE_IRQ, &icu_cascade); - setup_irq(INT2_CASCADE_IRQ, &icu_cascade); - setup_irq(INT3_CASCADE_IRQ, &icu_cascade); - setup_irq(INT4_CASCADE_IRQ, &icu_cascade); -} + cascade_irq(INT0_IRQ, icu_get_irq); + cascade_irq(INT1_IRQ, icu_get_irq); + cascade_irq(INT2_IRQ, icu_get_irq); + cascade_irq(INT3_IRQ, icu_get_irq); + cascade_irq(INT4_IRQ, icu_get_irq); -void __init arch_init_irq(void) -{ - mips_cpu_irq_init(MIPS_CPU_IRQ_BASE); - init_vr41xx_icu_irq(); - init_vr41xx_giuint_irq(); - - set_except_vector(0, vr41xx_handle_interrupt); + return 0; } + +core_initcall(vr41xx_icu_init); diff --git a/arch/mips/vr41xx/common/int-handler.S b/arch/mips/vr41xx/common/int-handler.S index 38ff89b505f2..272c13aee4fd 100644 --- a/arch/mips/vr41xx/common/int-handler.S +++ b/arch/mips/vr41xx/common/int-handler.S @@ -71,24 +71,24 @@ andi t1, t0, CAUSEF_IP3 # check for Int1 bnez t1, handle_int - li a0, 1 + li a0, 3 andi t1, t0, CAUSEF_IP4 # check for Int2 bnez t1, handle_int - li a0, 2 + li a0, 4 andi t1, t0, CAUSEF_IP5 # check for Int3 bnez t1, handle_int - li a0, 3 + li a0, 5 andi t1, t0, CAUSEF_IP6 # check for Int4 bnez t1, handle_int - li a0, 4 + li a0, 6 1: andi t1, t0, CAUSEF_IP2 # check for Int0 bnez t1, handle_int - li a0, 0 + li a0, 2 andi t1, t0, CAUSEF_IP0 # check for IP0 bnez t1, handle_irq diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c new file mode 100644 index 000000000000..43b214d39438 --- /dev/null +++ b/arch/mips/vr41xx/common/irq.c @@ -0,0 +1,94 @@ +/* + * Interrupt handing routines for NEC VR4100 series. + * + * Copyright (C) 2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <linux/interrupt.h> +#include <linux/module.h> + +#include <asm/irq_cpu.h> +#include <asm/system.h> +#include <asm/vr41xx/vr41xx.h> + +typedef struct irq_cascade { + int (*get_irq)(unsigned int, struct pt_regs *); +} irq_cascade_t; + +static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned; + +static struct irqaction cascade_irqaction = { + .handler = no_action, + .mask = CPU_MASK_NONE, + .name = "cascade", +}; + +int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *)) +{ + int retval = 0; + + if (irq >= NR_IRQS) + return -EINVAL; + + if (irq_cascade[irq].get_irq != NULL) + free_irq(irq, NULL); + + irq_cascade[irq].get_irq = get_irq; + + if (get_irq != NULL) { + retval = setup_irq(irq, &cascade_irqaction); + if (retval < 0) + irq_cascade[irq].get_irq = NULL; + } + + return retval; +} + +EXPORT_SYMBOL_GPL(cascade_irq); + +asmlinkage void irq_dispatch(unsigned int irq, struct pt_regs *regs) +{ + irq_cascade_t *cascade; + irq_desc_t *desc; + + if (irq >= NR_IRQS) { + atomic_inc(&irq_err_count); + return; + } + + cascade = irq_cascade + irq; + if (cascade->get_irq != NULL) { + unsigned int source_irq = irq; + desc = irq_desc + source_irq; + desc->handler->ack(source_irq); + irq = cascade->get_irq(irq, regs); + if (irq < 0) + atomic_inc(&irq_err_count); + else + irq_dispatch(irq, regs); + desc->handler->end(source_irq); + } else + do_IRQ(irq, regs); +} + +extern asmlinkage void vr41xx_handle_interrupt(void); + +void __init arch_init_irq(void) +{ + mips_cpu_irq_init(MIPS_CPU_IRQ_BASE); + + set_except_vector(0, vr41xx_handle_interrupt); +} diff --git a/arch/mips/vr41xx/tanbac-tb0226/setup.c b/arch/mips/vr41xx/common/type.c index 60027e5dea25..bcb5f71b5026 100644 --- a/arch/mips/vr41xx/tanbac-tb0226/setup.c +++ b/arch/mips/vr41xx/common/type.c @@ -1,7 +1,7 @@ /* - * setup.c, Setup for the TANBAC TB0226. + * type.c, System type for NEC VR4100 series. * - * Copyright (C) 2002-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> + * Copyright (C) 2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,5 +20,5 @@ const char *get_system_type(void) { - return "TANBAC TB0226"; + return "NEC VR4100 series"; } diff --git a/arch/mips/vr41xx/common/vrc4173.c b/arch/mips/vr41xx/common/vrc4173.c index 5475dd72e264..ba58764ef8ea 100644 --- a/arch/mips/vr41xx/common/vrc4173.c +++ b/arch/mips/vr41xx/common/vrc4173.c @@ -476,7 +476,7 @@ static inline int vrc4173_icu_init(int cascade_irq) if (cascade_irq < GIU_IRQ(0) || cascade_irq > GIU_IRQ(15)) return -EINVAL; - + vrc4173_outw(0, VRC4173_MSYSINT1REG); vr41xx_set_irq_trigger(GIU_IRQ_TO_PIN(cascade_irq), TRIGGER_LEVEL, SIGNAL_THROUGH); diff --git a/arch/mips/vr41xx/ibm-workpad/setup.c b/arch/mips/vr41xx/ibm-workpad/setup.c index cff44602d3d4..e4b34ad6ea61 100644 --- a/arch/mips/vr41xx/ibm-workpad/setup.c +++ b/arch/mips/vr41xx/ibm-workpad/setup.c @@ -23,11 +23,6 @@ #include <asm/io.h> #include <asm/vr41xx/workpad.h> -const char *get_system_type(void) -{ - return "IBM WorkPad z50"; -} - static int __init ibm_workpad_setup(void) { set_io_port_base(IO_PORT_BASE); diff --git a/arch/mips/vr41xx/nec-cmbvr4133/init.c b/arch/mips/vr41xx/nec-cmbvr4133/init.c index 87f06b3f5a9c..be590edb0b83 100644 --- a/arch/mips/vr41xx/nec-cmbvr4133/init.c +++ b/arch/mips/vr41xx/nec-cmbvr4133/init.c @@ -16,11 +16,6 @@ * Manish Lachwani (mlachwani@mvista.com) */ #include <linux/config.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/string.h> - -#include <asm/bootinfo.h> #ifdef CONFIG_ROCKHOPPER #include <asm/io.h> @@ -28,14 +23,7 @@ #define PCICONFDREG 0xaf000c14 #define PCICONFAREG 0xaf000c18 -#endif - -const char *get_system_type(void) -{ - return "NEC CMB-VR4133"; -} -#ifdef CONFIG_ROCKHOPPER void disable_pcnet(void) { u32 data; diff --git a/arch/mips/vr41xx/tanbac-tb0226/Makefile b/arch/mips/vr41xx/tanbac-tb0226/Makefile deleted file mode 100644 index 372f953d240b..000000000000 --- a/arch/mips/vr41xx/tanbac-tb0226/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the TANBAC TB0226 specific parts of the kernel -# - -obj-y += setup.o diff --git a/arch/mips/vr41xx/tanbac-tb0229/Makefile b/arch/mips/vr41xx/tanbac-tb0229/Makefile deleted file mode 100644 index 9c6b864ef2ef..000000000000 --- a/arch/mips/vr41xx/tanbac-tb0229/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the TANBAC TB0229(VR4131DIMM) specific parts of the kernel -# - -obj-y := setup.o diff --git a/arch/mips/vr41xx/tanbac-tb0229/setup.c b/arch/mips/vr41xx/tanbac-tb0229/setup.c deleted file mode 100644 index 5c1b757bfb0c..000000000000 --- a/arch/mips/vr41xx/tanbac-tb0229/setup.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * setup.c, Setup for the TANBAC TB0229 (VR4131DIMM) - * - * Copyright (C) 2002-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> - * - * Modified for TANBAC TB0229: - * Copyright (C) 2003 Megasolution Inc. <matsu@megasolution.jp> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -const char *get_system_type(void) -{ - return "TANBAC TB0229"; -} diff --git a/arch/mips/vr41xx/victor-mpc30x/Makefile b/arch/mips/vr41xx/victor-mpc30x/Makefile deleted file mode 100644 index a2e8086a31a6..000000000000 --- a/arch/mips/vr41xx/victor-mpc30x/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the Victor MP-C303/304 specific parts of the kernel -# - -obj-y += setup.o diff --git a/arch/mips/vr41xx/victor-mpc30x/setup.c b/arch/mips/vr41xx/victor-mpc30x/setup.c deleted file mode 100644 index f591e36726e6..000000000000 --- a/arch/mips/vr41xx/victor-mpc30x/setup.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * setup.c, Setup for the Victor MP-C303/304. - * - * Copyright (C) 2002-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -const char *get_system_type(void) -{ - return "Victor MP-C303/304"; -} diff --git a/arch/mips/vr41xx/zao-capcella/Makefile b/arch/mips/vr41xx/zao-capcella/Makefile deleted file mode 100644 index cf420197cd23..000000000000 --- a/arch/mips/vr41xx/zao-capcella/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the ZAO Networks Capcella specific parts of the kernel -# - -obj-y += setup.o diff --git a/arch/mips/vr41xx/zao-capcella/setup.c b/arch/mips/vr41xx/zao-capcella/setup.c deleted file mode 100644 index 17bade241fe2..000000000000 --- a/arch/mips/vr41xx/zao-capcella/setup.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * setup.c, Setup for the ZAO Networks Capcella. - * - * Copyright (C) 2002-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -const char *get_system_type(void) -{ - return "ZAO Networks Capcella"; -} |