diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2012-01-11 18:37:16 +0400 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2012-01-11 18:37:16 +0400 |
commit | c539ef7d355219c7b0e16cc302bf179fcad936b3 (patch) | |
tree | 1ef75df68f3eee8c195e67ddb605afb3e778b090 /arch/mips | |
parent | f467e4bfb50ca6af042f1b19b3556bd4aca854c3 (diff) | |
download | linux-c539ef7d355219c7b0e16cc302bf179fcad936b3.tar.xz |
MIPS: Set default pci cache line size.
On MIPS the generic PCI code has always defaulted to L1_CACHE_BYTES
because the architecutre PCI code did not provide a better default.
In particular on systems with S-caches or T-caches this was suboptimal.
Provide a better default by setting pci_dfl_cache_line_size based on
the size of the line size of the lowest level of the cache hierarchy.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/2982/
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/pci/pci.c | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 41af7fa2887b..8ac0d4841852 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -4,8 +4,11 @@ * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * - * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2011 Wind River Systems, + * written by Ralf Baechle (ralf@linux-mips.org) */ +#include <linux/bug.h> #include <linux/kernel.h> #include <linux/mm.h> #include <linux/bootmem.h> @@ -14,6 +17,8 @@ #include <linux/types.h> #include <linux/pci.h> +#include <asm/cpu-info.h> + /* * Indicate whether we respect the PCI setup left by the firmware. * @@ -150,10 +155,32 @@ out: "Skipping PCI bus scan due to resource conflict\n"); } +static void __init pcibios_set_cache_line_size(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned int lsize; + + /* + * Set PCI cacheline size to that of the highest level in the + * cache hierarchy. + */ + lsize = c->dcache.linesz; + lsize = c->scache.linesz ? : lsize; + lsize = c->tcache.linesz ? : lsize; + + BUG_ON(!lsize); + + pci_dfl_cache_line_size = lsize >> 2; + + pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize); +} + static int __init pcibios_init(void) { struct pci_controller *hose; + pcibios_set_cache_line_size(); + /* Scan all of the recorded PCI controllers. */ for (hose = hose_head; hose; hose = hose->next) pcibios_scanbus(hose); |