diff options
| author | Steven J. Hill <sjhill@mips.com> | 2012-08-03 19:26:04 +0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2012-10-11 13:05:03 +0400 |
| commit | ee80f7c73dc1b1f0ba9f82079c9bd1c0d1aedef8 (patch) | |
| tree | ef49eefa2ae08e015ebe526d10f81c7fe477d610 /arch/mips | |
| parent | f59a2d22a05272034e856b7a2dd7a3ab7864a2ae (diff) | |
| download | linux-ee80f7c73dc1b1f0ba9f82079c9bd1c0d1aedef8.tar.xz | |
MIPS: Add detection of DSP ASE Revision 2.
[ralf@linux-mips.org: This patch really only detects the ASE and passes its
existence on to userland via /proc/cpuinfo. The DSP ASE Rev 2. adds new
resources but no resources that would need management by the kernel.]
Signed-off-by: Steven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4165/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/include/asm/cpu-features.h | 4 | ||||
| -rw-r--r-- | arch/mips/include/asm/cpu.h | 1 | ||||
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 1 | ||||
| -rw-r--r-- | arch/mips/kernel/cpu-probe.c | 6 | ||||
| -rw-r--r-- | arch/mips/kernel/proc.c | 1 |
5 files changed, 11 insertions, 2 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 089125a6ae6a..c507b931b484 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -171,6 +171,10 @@ #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) #endif +#ifndef cpu_has_dsp2 +#define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P) +#endif + #ifndef cpu_has_mipsmt #define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) #endif diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 7dc0db8b9426..52c4e914f95a 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -332,6 +332,7 @@ enum cpu_type_enum { #define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ #define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ +#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */ #endif /* _ASM_CPU_H */ diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 04d7560dfafb..eb742895dcbe 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -592,6 +592,7 @@ #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) +#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index bd2809698e39..b1fb7af3c350 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -142,7 +142,7 @@ int __cpuinitdata mips_dsp_disabled; static int __init dsp_disable(char *s) { - cpu_data[0].ases &= ~MIPS_ASE_DSP; + cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); mips_dsp_disabled = 1; return 1; @@ -429,6 +429,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) c->options |= MIPS_CPU_RIXI; if (config3 & MIPS_CONF3_DSP) c->ases |= MIPS_ASE_DSP; + if (config3 & MIPS_CONF3_DSP2P) + c->ases |= MIPS_ASE_DSP2P; if (config3 & MIPS_CONF3_VINT) c->options |= MIPS_CPU_VINT; if (config3 & MIPS_CONF3_VEIC) @@ -1180,7 +1182,7 @@ __cpuinit void cpu_probe(void) c->options &= ~MIPS_CPU_FPU; if (mips_dsp_disabled) - c->ases &= ~MIPS_ASE_DSP; + c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); if (c->options & MIPS_CPU_FPU) { c->fpu_id = cpu_get_fpu_id(); diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 5542817c1b49..35cf2094f9ae 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -70,6 +70,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) cpu_has_mips3d ? " mips3d" : "", cpu_has_smartmips ? " smartmips" : "", cpu_has_dsp ? " dsp" : "", + cpu_has_dsp2 ? " dsp2" : "", cpu_has_mipsmt ? " mt" : "" ); seq_printf(m, "shadow register sets\t: %d\n", |