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authorRalf Baechle <ralf@linux-mips.org>2010-03-23 02:02:43 +0300
committerRalf Baechle <ralf@linux-mips.org>2010-04-12 20:26:19 +0400
commit8d9df29db273ab9a330828f4f4f6669d293a730a (patch)
tree7f5e9c87125d53fc2a512be150b01f6116918b3f /arch/mips/sibyte
parent9538ca636f2fa28ae1514327328e2869f0215981 (diff)
downloadlinux-8d9df29db273ab9a330828f4f4f6669d293a730a.tar.xz
MIPS: Sibyte: Apply M3 workaround only on affected chip types and versions.
Previously it was unconditionally used on all Sibyte family SOCs. The M3 bug has to be handled in the TLB exception handler which is extremly performance sensitive, so this modification is expected to deliver around 2-3% performance improvment. This is important as required changes to the M3 workaround will make it more costly. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/sibyte')
-rw-r--r--arch/mips/sibyte/sb1250/setup.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c
index 0444da1e23c2..92da3155ce07 100644
--- a/arch/mips/sibyte/sb1250/setup.c
+++ b/arch/mips/sibyte/sb1250/setup.c
@@ -87,6 +87,21 @@ static int __init setup_bcm1250(void)
return ret;
}
+int sb1250_m3_workaround_needed(void)
+{
+ switch (soc_type) {
+ case K_SYS_SOC_TYPE_BCM1250:
+ case K_SYS_SOC_TYPE_BCM1250_ALT:
+ case K_SYS_SOC_TYPE_BCM1250_ALT2:
+ case K_SYS_SOC_TYPE_BCM1125:
+ case K_SYS_SOC_TYPE_BCM1125H:
+ return soc_pass < K_SYS_REVISION_BCM1250_C0;
+
+ default:
+ return 0;
+ }
+}
+
static int __init setup_bcm112x(void)
{
int ret = 0;