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| author | Stefan Agner <stefan@agner.ch> | 2020-12-07 20:58:03 +0300 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2020-12-07 22:12:50 +0300 |
| commit | 9e454e37dc7c0ee9e108d70b983e7a71332aedff (patch) | |
| tree | 6872ff13c62d8f1b150d0519f7c15f5f792eb99c /arch/mips/sgi-ip30 | |
| parent | 3d07c3b3a886fefd583c1b485b5e4e3c4e2da493 (diff) | |
| download | linux-9e454e37dc7c0ee9e108d70b983e7a71332aedff.tar.xz | |
arm64: dts: meson: g12b: w400: fix PHY deassert timing requirements
According to the datasheet (Rev. 1.9) the RTL8211F requires at least
72ms "for internal circuits settling time" before accessing the PHY
egisters. On similar boards with the same PHY this fixes an issue where
Ethernet link would not come up when using ip link set down/up.
Fixes: 2cd2310fca4c ("arm64: dts: meson-g12b-ugoos-am6: add initial device-tree")
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/46298e66572784c44f873f1b71cc4ab3d8fc5aa6.1607363522.git.stefan@agner.ch
Diffstat (limited to 'arch/mips/sgi-ip30')
0 files changed, 0 insertions, 0 deletions