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| author | Paul Burton <paul.burton@imgtec.com> | 2016-08-19 20:13:36 +0300 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2017-01-03 18:48:40 +0300 |
| commit | 48ed33c1b3737eb1324c1ae023a8eeccad60cef9 (patch) | |
| tree | 2f0bba73f2155877df0790bbc863036f89bfb9e2 /arch/mips/ralink | |
| parent | d66f99bc46925831236cf2335fcc6087d34e2195 (diff) | |
| download | linux-48ed33c1b3737eb1324c1ae023a8eeccad60cef9.tar.xz | |
MIPS: sc-mips: L2 cache is inclusive of L1 dcache for CM3
In systems with CM3 & higher, the L2 cache is inclusive of the L1
dcache. Indicate this such that cpu_has_inclusive_pcaches evaluates true
and we avoid some unnecessary cache ops during DMA cache maintenance.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14018/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/ralink')
0 files changed, 0 insertions, 0 deletions