diff options
| author | Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> | 2016-06-03 11:35:00 +0300 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-07-24 13:41:22 +0300 |
| commit | 645c7827e67ca0f06e232a1106af71c531460504 (patch) | |
| tree | 3cda7b42e602ca67e7e8007487ba47f2cfab6099 /arch/mips/pistachio | |
| parent | 666dc3676473e025be1fd94395f16be31d83168e (diff) | |
| download | linux-645c7827e67ca0f06e232a1106af71c531460504.tar.xz | |
MIPS: Pistachio: Remove plat_setup_iocoherency
The Pistachio SoC does not have an IOCU. Hence, DMA is non-coherent.
Remove the function checking for iocoherency and select
CONFIG_DMA_NONCOHERENT in Kconfig
This code is probably accidentally inherited from Malta.
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: James Hartley <james.hartley@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13433/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pistachio')
| -rw-r--r-- | arch/mips/pistachio/init.c | 25 |
1 files changed, 0 insertions, 25 deletions
diff --git a/arch/mips/pistachio/init.c b/arch/mips/pistachio/init.c index ab79828230ab..387b9df1bc7c 100644 --- a/arch/mips/pistachio/init.c +++ b/arch/mips/pistachio/init.c @@ -60,29 +60,6 @@ const char *get_system_type(void) return sys_type; } -static void __init plat_setup_iocoherency(void) -{ - /* - * Kernel has been configured with software coherency - * but we might choose to turn it off and use hardware - * coherency instead. - */ - if (mips_cm_numiocu() != 0) { - /* Nothing special needs to be done to enable coherency */ - pr_info("CMP IOCU detected\n"); - hw_coherentio = 1; - if (coherentio == 0) - pr_info("Hardware DMA cache coherency disabled\n"); - else - pr_info("Hardware DMA cache coherency enabled\n"); - } else { - if (coherentio == 1) - pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n"); - else - pr_info("Software DMA cache coherency enabled\n"); - } -} - void __init *plat_get_fdt(void) { if (fw_arg0 != -2) @@ -93,8 +70,6 @@ void __init *plat_get_fdt(void) void __init plat_mem_setup(void) { __dt_setup_arch(plat_get_fdt()); - - plat_setup_iocoherency(); } #define DEFAULT_CPC_BASE_ADDR 0x1bde0000 |