diff options
| author | John Crispin <john@phrozen.org> | 2017-02-20 12:29:44 +0300 |
|---|---|---|
| committer | James Hogan <jhogan@kernel.org> | 2017-11-13 16:01:50 +0300 |
| commit | b54fcf6ae1157b35504dde93581db0810c03b4b7 (patch) | |
| tree | c09c78926ab733fbd59a9bafc688b448fb4983a9 /arch/mips/pci | |
| parent | 8593b18ad348733b5d5ddfa0c79dcabf51dff308 (diff) | |
| download | linux-b54fcf6ae1157b35504dde93581db0810c03b4b7.tar.xz | |
MIPS: pci: Make use of the BIT() macro inside the mt7620 driver
There are a few defines that manully shift a bit. Change these to using
the BIT() macro.
Signed-off-by: John Crispin <john@phrozen.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/15322/
Signed-off-by: James Hogan <jhogan@kernel.org>
Diffstat (limited to 'arch/mips/pci')
| -rw-r--r-- | arch/mips/pci/pci-mt7620.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/mips/pci/pci-mt7620.c b/arch/mips/pci/pci-mt7620.c index 1a0b80a1cc4a..407f155f0bb6 100644 --- a/arch/mips/pci/pci-mt7620.c +++ b/arch/mips/pci/pci-mt7620.c @@ -35,11 +35,11 @@ #define PPLL_CFG1 0x9c #define PPLL_DRV 0xa0 -#define PDRV_SW_SET (1<<31) -#define LC_CKDRVPD (1<<19) -#define LC_CKDRVOHZ (1<<18) -#define LC_CKDRVHZ (1<<17) -#define LC_CKTEST (1<<16) +#define PDRV_SW_SET BIT(31) +#define LC_CKDRVPD BIT(19) +#define LC_CKDRVOHZ BIT(18) +#define LC_CKDRVHZ BIT(17) +#define LC_CKTEST BIT(16) /* PCI Bridge registers */ #define RALINK_PCI_PCICFG_ADDR 0x00 @@ -65,7 +65,7 @@ #define PCIEPHY0_CFG 0x90 #define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498 -#define RALINK_PCIE0_CLK_EN (1 << 26) +#define RALINK_PCIE0_CLK_EN BIT(26) #define BUSY 0x80000000 #define WAITRETRY_MAX 10 |