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authorAndrea Gelmini <andrea.gelmini@gelma.net>2016-05-21 15:00:11 +0300
committerRalf Baechle <ralf@linux-mips.org>2016-05-28 13:35:07 +0300
commit87fd4e2692a2add7726fb5a497c617c99071de34 (patch)
tree12c3acd76fd651e28f4911ebcede2233c7db534e /arch/mips/pci
parente904b94a06c77a4241df7ba239c3b5fd1ddb1809 (diff)
downloadlinux-87fd4e2692a2add7726fb5a497c617c99071de34.tar.xz
MIPS: IP27: Fix typo
Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13320/ Patchwork: https://patchwork.linux-mips.org/patch/13335/ Patchwork: https://patchwork.linux-mips.org/patch/13336/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci')
-rw-r--r--arch/mips/pci/ops-bridge.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/pci/ops-bridge.c b/arch/mips/pci/ops-bridge.c
index 438319465cb4..57e1463fcd02 100644
--- a/arch/mips/pci/ops-bridge.c
+++ b/arch/mips/pci/ops-bridge.c
@@ -33,9 +33,9 @@ static u32 emulate_ioc3_cfg(int where, int size)
* The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
* not really documented, so right now I can't write code which uses it.
* Therefore we use type 0 accesses for now even though they won't work
- * correcly for PCI-to-PCI bridges.
+ * correctly for PCI-to-PCI bridges.
*
- * The function is complicated by the ultimate brokeness of the IOC3 chip
+ * The function is complicated by the ultimate brokenness of the IOC3 chip
* which is used in SGI systems. The IOC3 can only handle 32-bit PCI
* accesses and does only decode parts of it's address space.
*/