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| author | Wu Zhangjin <wuzhangjin@gmail.com> | 2010-05-06 20:59:46 +0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2010-05-16 00:59:54 +0400 |
| commit | 4e73238d163c6fcf001264832701d2a6d4927672 (patch) | |
| tree | bf8b9aa38ffec794d44cb1a81ee99c52e4d6b5f0 /arch/mips/oprofile/op_model_loongson2.c | |
| parent | 46afb8296c2494bfce17064124b253eb9b176ef9 (diff) | |
| download | linux-4e73238d163c6fcf001264832701d2a6d4927672.tar.xz | |
MIPS: Oprofile: Fix Loongson irq handler
The interrupt enable bit for the performance counters is in the Control
Register $24, not in the counter register.
loongson2_perfcount_handler(), we need to use
Reported-by: Xu Hengyang <hengyang@mail.ustc.edu.cn>
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/1198/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
Diffstat (limited to 'arch/mips/oprofile/op_model_loongson2.c')
| -rw-r--r-- | arch/mips/oprofile/op_model_loongson2.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c index 29e2326b6257..fa3bf661ae29 100644 --- a/arch/mips/oprofile/op_model_loongson2.c +++ b/arch/mips/oprofile/op_model_loongson2.c @@ -122,7 +122,7 @@ static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id) */ /* Check whether the irq belongs to me */ - enabled = read_c0_perfcnt() & LOONGSON2_PERFCNT_INT_EN; + enabled = read_c0_perfctrl() & LOONGSON2_PERFCNT_INT_EN; if (!enabled) return IRQ_NONE; enabled = reg.cnt1_enabled | reg.cnt2_enabled; |