diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-06-16 21:22:31 +0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-06-16 21:22:31 +0400 |
| commit | 626a16c16e13e4afaba382bfc0354a3555f5231c (patch) | |
| tree | 7a0a0c1f8e19b18c98757a076a4a03f294b75d10 /arch/mips/nxp/pnx8550/jbs | |
| parent | e53d6a152793a38aa334d6f7a4850642ae45cedc (diff) | |
| parent | dab8c6deaf1d654d09c3de8bd4c286d424df255a (diff) | |
| download | linux-626a16c16e13e4afaba382bfc0354a3555f5231c.tar.xz | |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
[MIPS] Au1200: MMC resource size off by one
[MIPS] TANBAC: Update defconfig
[MIPS] Vr41xx: Initialize PCI io_map_base
[MIPS] Malta: Always compile MTD platform device registration code.
[MIPS] Malta: Fix build errors for 64-bit kernels
[MIPS] Lasat: sysctl fixup
[MIPS] Fix buggy use of kmap_coherent.
[MIPS] Lasat: bring back from the dead
[MIPS] vpe_id is required for VSMP and SMTC builds
[MIPS] Export smp_call_function and smp_call_function_single.
[MIPS] Bring the SWARM defconfig up to date
[MIPS] Sibyte: Build RTC support as an object
[MIPS] Fix the fix for divide by zero error in build_{clear,copy}_page
[MIPS] Fix build for PNX platforms.
[MIPS] Add RM200 with R5000 CPU to known ARC machines
[MIPS] Better load address for big endian SNI RM
[MIPS] SB1250: Initialize io_map_base
[MIPS] Alchemy: Add au1500 reserved interrupt
[MIPS] Export empty_zero_page for sake of the ext4 module.
Diffstat (limited to 'arch/mips/nxp/pnx8550/jbs')
| -rw-r--r-- | arch/mips/nxp/pnx8550/jbs/board_setup.c | 11 |
1 files changed, 1 insertions, 10 deletions
diff --git a/arch/mips/nxp/pnx8550/jbs/board_setup.c b/arch/mips/nxp/pnx8550/jbs/board_setup.c index f92826e0096d..57dd903ca408 100644 --- a/arch/mips/nxp/pnx8550/jbs/board_setup.c +++ b/arch/mips/nxp/pnx8550/jbs/board_setup.c @@ -47,16 +47,7 @@ void __init board_setup(void) { - unsigned long config0, configpr; - - config0 = read_c0_config(); - - /* clear all three cache coherency fields */ - config0 &= ~(0x7 | (7<<25) | (7<<28)); - config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) | - (CONF_CM_DEFAULT<<28)); - write_c0_config(config0); - BARRIER; + unsigned long configpr; configpr = read_c0_config7(); configpr |= (1<<19); /* enable tlb */ |