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authorJayachandran C <jchandra@broadcom.com>2014-04-29 18:37:49 +0400
committerRalf Baechle <ralf@linux-mips.org>2014-05-30 18:49:02 +0400
commit5874743ea8479b780799927f25580ef134547f0f (patch)
treee3e0e661306fc728d06b7a5e8bb8265a91e4d9d3 /arch/mips/netlogic/common/reset.S
parent0d57eba02d6f0685e61763502962fcf00fd4e4cc (diff)
downloadlinux-5874743ea8479b780799927f25580ef134547f0f.tar.xz
MIPS: Netlogic: Use PRID_IMP_MASK macro
Use PRID_IMP_MASK macro instead of 0xff00 to extract the processor type. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6868/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/netlogic/common/reset.S')
-rw-r--r--arch/mips/netlogic/common/reset.S5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S
index 13c1bc5b5988..5b60b469da15 100644
--- a/arch/mips/netlogic/common/reset.S
+++ b/arch/mips/netlogic/common/reset.S
@@ -35,6 +35,7 @@
#include <asm/asm.h>
#include <asm/asm-offsets.h>
+#include <asm/cpu.h>
#include <asm/cacheops.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
@@ -92,7 +93,7 @@
*/
.macro xlp_flush_l1_dcache
mfc0 t0, CP0_EBASE, 0
- andi t0, t0, 0xff00
+ andi t0, t0, PRID_IMP_MASK
slt t1, t0, 0x1200
beqz t1, 15f
nop
@@ -171,7 +172,7 @@ FEXPORT(nlm_reset_entry)
1: /* Entry point on core wakeup */
mfc0 t0, CP0_EBASE, 0 /* processor ID */
- andi t0, 0xff00
+ andi t0, PRID_IMP_MASK
li t1, 0x1500 /* XLP 9xx */
beq t0, t1, 2f /* does not need to set coherent */
nop