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author | Linus Torvalds <torvalds@linux-foundation.org> | 2017-05-12 19:56:30 +0300 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2017-05-12 19:56:30 +0300 |
commit | ac3c4aa248c5b5390c40fad1ceb0a15a53f57a36 (patch) | |
tree | a7b09cc6d8a9ec28bfb7d2ab7d280dd8e61bfb5e /arch/mips/mti-malta | |
parent | 0ba1c1950c320fcfdfe3dbc7470884e4a390083c (diff) | |
parent | 3e441845caf1c9591b5b961f34ff1a37d023c9e2 (diff) | |
download | linux-ac3c4aa248c5b5390c40fad1ceb0a15a53f57a36.tar.xz |
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from James Hogan:
"math-emu:
- Add missing clearing of BLTZALL and BGEZALL emulation counters
- Fix BC1EQZ and BC1NEZ condition handling
- Fix BLEZL and BGTZL identification
BPF:
- Add JIT support for SKF_AD_HATYPE
- Use unsigned access for unsigned SKB fields
- Quit clobbering callee saved registers in JIT code
- Fix multiple problems in JIT skb access helpers
Loongson 3:
- Select MIPS_L1_CACHE_SHIFT_6
Octeon:
- Remove vestiges of CONFIG_CAVIUM_OCTEON_2ND_KERNEL
- Remove unused L2C types and macros.
- Remove unused SLI types and macros.
- Fix compile error when USB is not enabled.
- Octeon: Remove unused PCIERCX types and macros.
- Octeon: Clean up platform code.
SNI:
- Remove recursive include of cpu-feature-overrides.h
Sibyte:
- Export symbol periph_rev to sb1250-mac network driver.
- Fix Kconfig warning.
Generic platform:
- Enable Root FS on NFS in generic_defconfig
SMP-MT:
- Use CPU interrupt controller IPI IRQ domain support
UASM:
- Add support for LHU for uasm.
- Remove needless ISA abstraction
mm:
- Add 48-bit VA space and 4-level page tables for 4K pages.
PCI:
- Add controllers before the specified head
irqchip driver for MIPS CPU:
- Replace magic 0x100 with IE_SW0
- Prepare for non-legacy IRQ domains
- Introduce IPI IRQ domain support
MAINTAINERS:
- Update email-id of Rahul Bedarkar
NET:
- sb1250-mac: Add missing MODULE_LICENSE()
CPUFREQ:
- Loongson2: drop set_cpus_allowed_ptr()
Misc:
- Disable Werror when W= is set
- Opt into HAVE_COPY_THREAD_TLS
- Enable GENERIC_CPU_AUTOPROBE
- Use common outgoing-CPU-notification code
- Remove dead define of ST_OFF
- Remove CONFIG_ARCH_HAS_ILOG2_U{32,64}
- Stengthen IPI IRQ domain sanity check
- Remove confusing else statement in __do_page_fault()
- Don't unnecessarily include kmalloc.h into <asm/cache.h>.
- Delete unused definition of SMP_CACHE_SHIFT.
- Delete redundant definition of SMP_CACHE_BYTES"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (39 commits)
MIPS: Sibyte: Fix Kconfig warning.
MIPS: Sibyte: Export symbol periph_rev to sb1250-mac network driver.
NET: sb1250-mac: Add missing MODULE_LICENSE()
MAINTAINERS: Update email-id of Rahul Bedarkar
MIPS: Remove confusing else statement in __do_page_fault()
MIPS: Stengthen IPI IRQ domain sanity check
MIPS: smp-mt: Use CPU interrupt controller IPI IRQ domain support
irqchip: mips-cpu: Introduce IPI IRQ domain support
irqchip: mips-cpu: Prepare for non-legacy IRQ domains
irqchip: mips-cpu: Replace magic 0x100 with IE_SW0
MIPS: Remove CONFIG_ARCH_HAS_ILOG2_U{32,64}
MIPS: generic: Enable Root FS on NFS in generic_defconfig
MIPS: mach-rm: Remove recursive include of cpu-feature-overrides.h
MIPS: Opt into HAVE_COPY_THREAD_TLS
CPUFREQ: Loongson2: drop set_cpus_allowed_ptr()
MIPS: uasm: Remove needless ISA abstraction
MIPS: Remove dead define of ST_OFF
MIPS: Use common outgoing-CPU-notification code
MIPS: math-emu: Fix BC1EQZ and BC1NEZ condition handling
MIPS: r2-on-r6-emu: Clear BLTZALL and BGEZALL debugfs counters
...
Diffstat (limited to 'arch/mips/mti-malta')
-rw-r--r-- | arch/mips/mti-malta/malta-int.c | 83 |
1 files changed, 4 insertions, 79 deletions
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index 54f56d5a96c4..b0f9b188e833 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -145,56 +145,6 @@ static irqreturn_t corehi_handler(int irq, void *dev_id) return IRQ_HANDLED; } -#ifdef CONFIG_MIPS_MT_SMP - -#define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */ -#define C_RESCHED C_SW0 -#define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */ -#define C_CALL C_SW1 -static int cpu_ipi_resched_irq, cpu_ipi_call_irq; - -static void ipi_resched_dispatch(void) -{ - do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ); -} - -static void ipi_call_dispatch(void) -{ - do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ); -} - -static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) -{ -#ifdef CONFIG_MIPS_VPE_APSP_API_CMP - if (aprp_hook) - aprp_hook(); -#endif - - scheduler_ipi(); - - return IRQ_HANDLED; -} - -static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) -{ - generic_smp_call_function_interrupt(); - - return IRQ_HANDLED; -} - -static struct irqaction irq_resched = { - .handler = ipi_resched_interrupt, - .flags = IRQF_PERCPU, - .name = "IPI_resched" -}; - -static struct irqaction irq_call = { - .handler = ipi_call_interrupt, - .flags = IRQF_PERCPU, - .name = "IPI_call" -}; -#endif /* CONFIG_MIPS_MT_SMP */ - static struct irqaction corehi_irqaction = { .handler = corehi_handler, .name = "CoreHi", @@ -222,12 +172,6 @@ static msc_irqmap_t msc_eicirqmap[] __initdata = { static int msc_nr_eicirqs __initdata = ARRAY_SIZE(msc_eicirqmap); -void __init arch_init_ipiirq(int irq, struct irqaction *action) -{ - setup_irq(irq, action); - irq_set_handler(irq, handle_percpu_irq); -} - void __init arch_init_irq(void) { int corehi_irq; @@ -273,30 +217,11 @@ void __init arch_init_irq(void) if (gic_present) { corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI; + } else if (cpu_has_veic) { + set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch); + corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI; } else { -#if defined(CONFIG_MIPS_MT_SMP) - /* set up ipi interrupts */ - if (cpu_has_veic) { - set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch); - set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch); - cpu_ipi_resched_irq = MSC01E_INT_SW0; - cpu_ipi_call_irq = MSC01E_INT_SW1; - } else { - cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + - MIPS_CPU_IPI_RESCHED_IRQ; - cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + - MIPS_CPU_IPI_CALL_IRQ; - } - arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched); - arch_init_ipiirq(cpu_ipi_call_irq, &irq_call); -#endif - if (cpu_has_veic) { - set_vi_handler(MSC01E_INT_COREHI, - corehi_irqdispatch); - corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI; - } else { - corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI; - } + corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI; } setup_irq(corehi_irq, &corehi_irqaction); |