diff options
author | Paul Burton <paul.burton@imgtec.com> | 2014-01-15 14:31:54 +0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2014-03-27 02:09:06 +0400 |
commit | 237036de6540a377268db5bb2b9c8efdccbe51c1 (patch) | |
tree | 81a76206b8b67bb523d6994131faceeb62cf75e1 /arch/mips/mti-malta/malta-int.c | |
parent | 0ee958e102b62b418c2fb46c3439d4262067a5fc (diff) | |
download | linux-237036de6540a377268db5bb2b9c8efdccbe51c1.tar.xz |
MIPS: Malta: Make use of generic CM support
Remove the Malta-specific CM probe code and instead make use of the
newly added generic CM code.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6364/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mti-malta/malta-int.c')
-rw-r--r-- | arch/mips/mti-malta/malta-int.c | 70 |
1 files changed, 13 insertions, 57 deletions
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index ca3e3a46a42f..93103f81bf57 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -26,6 +26,7 @@ #include <asm/i8259.h> #include <asm/irq_cpu.h> #include <asm/irq_regs.h> +#include <asm/mips-cm.h> #include <asm/mips-boards/malta.h> #include <asm/mips-boards/maltaint.h> #include <asm/gt64120.h> @@ -33,13 +34,10 @@ #include <asm/mips-boards/msc01_pci.h> #include <asm/msc01_ic.h> #include <asm/gic.h> -#include <asm/gcmpregs.h> #include <asm/setup.h> #include <asm/rtlx.h> -int gcmp_present = -1; static unsigned long _msc01_biu_base; -static unsigned long _gcmp_base; static unsigned int ipi_map[NR_CPUS]; static DEFINE_RAW_SPINLOCK(mips_irq_lock); @@ -418,48 +416,6 @@ static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { }; #undef X -/* - * GCMP needs to be detected before any SMP initialisation - */ -int __init gcmp_probe(unsigned long addr, unsigned long size) -{ - if ((mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) && - (mips_revision_sconid != MIPS_REVISION_SCON_GT64120)) { - gcmp_present = 0; - pr_debug("GCMP NOT present\n"); - return gcmp_present; - } - - if (gcmp_present >= 0) - return gcmp_present; - - _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, - GCMP_ADDRSPACE_SZ); - _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, - MSC01_BIU_ADDRSPACE_SZ); - gcmp_present = ((GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == - GCMP_BASE_ADDR); - - if (gcmp_present) - pr_debug("GCMP present\n"); - return gcmp_present; -} - -/* Return the number of IOCU's present */ -int __init gcmp_niocu(void) -{ - return gcmp_present ? ((GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> - GCMP_GCB_GC_NUMIOCU_SHF) : 0; -} - -/* Set GCMP region attributes */ -void __init gcmp_setregion(int region, unsigned long base, - unsigned long mask, int type) -{ - GCMPGCBn(CMxBASE, region) = base; - GCMPGCBn(CMxMASK, region) = mask | type; -} - #if defined(CONFIG_MIPS_MT_SMP) static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin) { @@ -496,8 +452,8 @@ void __init arch_init_irq(void) if (!cpu_has_veic) mips_cpu_irq_init(); - if (gcmp_present) { - GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK; + if (mips_cm_present()) { + write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK); gic_present = 1; } else { if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) { @@ -584,7 +540,7 @@ void __init arch_init_irq(void) #endif gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); - if (!gcmp_present) { + if (!mips_cm_present()) { /* Enable the GIC */ i = REG(_msc01_biu_base, MSC01_SC_CFG); REG(_msc01_biu_base, MSC01_SC_CFG) = @@ -708,16 +664,16 @@ int malta_be_handler(struct pt_regs *regs, int is_fixup) /* This duplicates the handling in do_be which seems wrong */ int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL; - if (gcmp_present) { - unsigned long cm_error = GCMPGCB(GCMEC); - unsigned long cm_addr = GCMPGCB(GCMEA); - unsigned long cm_other = GCMPGCB(GCMEO); + if (mips_cm_present()) { + unsigned long cm_error = read_gcr_error_cause(); + unsigned long cm_addr = read_gcr_error_addr(); + unsigned long cm_other = read_gcr_error_mult(); unsigned long cause, ocause; char buf[256]; - cause = (cm_error & GCMP_GCB_GMEC_ERROR_TYPE_MSK); + cause = cm_error & CM_GCR_ERROR_CAUSE_ERRTYPE_MSK; if (cause != 0) { - cause >>= GCMP_GCB_GMEC_ERROR_TYPE_SHF; + cause >>= CM_GCR_ERROR_CAUSE_ERRTYPE_SHF; if (cause < 16) { unsigned long cca_bits = (cm_error >> 15) & 7; unsigned long tr_bits = (cm_error >> 12) & 7; @@ -748,8 +704,8 @@ int malta_be_handler(struct pt_regs *regs, int is_fixup) mcmd[cmd_bits], sport_bits); } - ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >> - GCMP_GCB_GMEO_ERROR_2ND_SHF; + ocause = (cm_other & CM_GCR_ERROR_MULT_ERR2ND_MSK) >> + CM_GCR_ERROR_MULT_ERR2ND_SHF; pr_err("CM_ERROR=%08lx %s <%s>\n", cm_error, causes[cause], buf); @@ -757,7 +713,7 @@ int malta_be_handler(struct pt_regs *regs, int is_fixup) pr_err("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]); /* reprime cause register */ - GCMPGCB(GCMEC) = 0; + write_gcr_error_cause(0); } } |