diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2015-03-25 15:18:27 +0300 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2015-04-10 16:41:49 +0300 |
commit | 9eaffa84a8a46adab065c983401fc9d5949c958f (patch) | |
tree | e61ad607c8fee9f700f3f01b0cef26e0bbc09016 /arch/mips/mm | |
parent | f05ff43355e6997c18f82ddcee370a6e5f8643ce (diff) | |
download | linux-9eaffa84a8a46adab065c983401fc9d5949c958f.tar.xz |
Revert "MIPS: Avoid pipeline stalls on some MIPS32R2 cores."
For a discussion, see http://patchwork.linux-mips.org/patch/9539/.
This reverts commit 625c0a21700bdb90844d926a1508a17a77e369c9.
Diffstat (limited to 'arch/mips/mm')
-rw-r--r-- | arch/mips/mm/tlbex.c | 21 |
1 files changed, 2 insertions, 19 deletions
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 7709920e0cef..971b1ee51234 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -512,26 +512,9 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l, case tlb_indexed: tlbw = uasm_i_tlbwi; break; } - if (cpu_has_mips_r2_exec_hazard) { - /* - * The architecture spec says an ehb is required here, - * but a number of cores do not have the hazard and - * using an ehb causes an expensive pipeline stall. - */ - switch (current_cpu_type()) { - case CPU_M14KC: - case CPU_74K: - case CPU_1074K: - case CPU_PROAPTIV: - case CPU_P5600: - case CPU_M5150: - case CPU_QEMU_GENERIC: - break; - - default: + if (cpu_has_mips_r2_r6) { + if (cpu_has_mips_r2_exec_hazard) uasm_i_ehb(p); - break; - } tlbw(p); return; } |