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| author | Florian Fainelli <f.fainelli@gmail.com> | 2016-04-04 20:55:36 +0300 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-05-13 15:02:07 +0300 |
| commit | f675843ddfdfdf467d08cc922201614a149e439e (patch) | |
| tree | 286abe58685334ae877e41779027d885c8597e43 /arch/mips/mm/c-r4k.c | |
| parent | 73c4ca047f440c79f545bc6133e3033f754cd239 (diff) | |
| download | linux-f675843ddfdfdf467d08cc922201614a149e439e.tar.xz | |
MIPS: BMIPS: local_r4k___flush_cache_all needs to blast S-cache
local_r4k___flush_cache_all() is missing a special check for BMIPS5000
processors, we need to blast the S-cache, just like other MTI processors
since we have an inclusive cache. We also need an additional __sync() to
make sure this is completed.
Fixes: d74b0172e4e2c ("MIPS: BMIPS: Add special cache handling in c-r4k.c")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13012/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 226516d9c851..6f43bdf9a679 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -447,6 +447,11 @@ static inline void local_r4k___flush_cache_all(void * args) r4k_blast_scache(); break; + case CPU_BMIPS5000: + r4k_blast_scache(); + __sync(); + break; + default: r4k_blast_dcache(); r4k_blast_icache(); |