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| author | H. Peter Anvin <hpa@linux.intel.com> | 2012-01-20 00:56:50 +0400 |
|---|---|---|
| committer | H. Peter Anvin <hpa@linux.intel.com> | 2012-01-20 00:56:50 +0400 |
| commit | 282f445a779ed76fca9884fe377bf56a3088b208 (patch) | |
| tree | d9abcf526baee0100672851e0a8894c19e762a39 /arch/mips/mm/c-r4k.c | |
| parent | 68f30fbee19cc67849b9fa8e153ede70758afe81 (diff) | |
| parent | 90a4c0f51e8e44111a926be6f4c87af3938a79c3 (diff) | |
| download | linux-282f445a779ed76fca9884fe377bf56a3088b208.tar.xz | |
Merge remote-tracking branch 'linus/master' into x86/urgent
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index a79fe9aa7721..4f9eb0b23036 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1235,6 +1235,9 @@ static void __cpuinit setup_scache(void) loongson2_sc_init(); return; #endif + case CPU_XLP: + /* don't need to worry about L2, fully coherent */ + return; default: if (c->isa_level == MIPS_CPU_ISA_M32R1 || |