diff options
| author | Huacai Chen <chenhc@lemote.com> | 2015-04-21 05:00:35 +0300 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-06-21 22:53:59 +0300 |
| commit | 30ad29bb48881ee11f5daf30c6fc50292ae08c57 (patch) | |
| tree | d899b18a17e6269123ff2795f2e6d832523f1fb9 /arch/mips/loongson64/loongson-3/smp.h | |
| parent | abcc82b19fa9b4f41e02f28715005851b580163d (diff) | |
| download | linux-30ad29bb48881ee11f5daf30c6fc50292ae08c57.tar.xz | |
MIPS: Loongson: Naming style cleanup and rework
Currently, code of Loongson-2/3 is under loongson directory and code of
Loongson-1 is under loongson1 directory. Besides, there are Kconfig
options such as MACH_LOONGSON and MACH_LOONGSON1. This naming style is
very ugly and confusing. Since Loongson-2/3 are both 64-bit general-
purpose CPU while Loongson-1 is 32-bit SoC, we rename both file names
and Kconfig symbols from loongson/loongson1 to loongson64/loongson32.
[ralf@linux-mips.org: Resolve a number of simple conflicts.]
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Kelvin Cheung <keguang.zhang@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/9790/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/loongson64/loongson-3/smp.h')
| -rw-r--r-- | arch/mips/loongson64/loongson-3/smp.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/mips/loongson64/loongson-3/smp.h b/arch/mips/loongson64/loongson-3/smp.h new file mode 100644 index 000000000000..d98ff654b7d7 --- /dev/null +++ b/arch/mips/loongson64/loongson-3/smp.h @@ -0,0 +1,30 @@ +#ifndef __LOONGSON_SMP_H_ +#define __LOONGSON_SMP_H_ + +/* for Loongson-3 smp support */ +extern unsigned long long smp_group[4]; + +/* 4 groups(nodes) in maximum in numa case */ +#define SMP_CORE_GROUP0_BASE (smp_group[0]) +#define SMP_CORE_GROUP1_BASE (smp_group[1]) +#define SMP_CORE_GROUP2_BASE (smp_group[2]) +#define SMP_CORE_GROUP3_BASE (smp_group[3]) + +/* 4 cores in each group(node) */ +#define SMP_CORE0_OFFSET 0x000 +#define SMP_CORE1_OFFSET 0x100 +#define SMP_CORE2_OFFSET 0x200 +#define SMP_CORE3_OFFSET 0x300 + +/* ipi registers offsets */ +#define STATUS0 0x00 +#define EN0 0x04 +#define SET0 0x08 +#define CLEAR0 0x0c +#define STATUS1 0x10 +#define MASK1 0x14 +#define SET1 0x18 +#define CLEAR1 0x1c +#define BUF 0x20 + +#endif |