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authorWu Zhangjin <wuzhangjin@gmail.com>2010-07-24 05:22:13 +0400
committerRalf Baechle <ralf@linux-mips.org>2010-08-05 16:26:23 +0400
commitb8c7428af023c4cc37b8651e309713c1f4d9a18e (patch)
treeb3ed6ba799a19e545696759722b0722072202506 /arch/mips/loongson/fuloong-2e
parent4c076fb41ac93bc0cbd55f2a731cc31337804acb (diff)
downloadlinux-b8c7428af023c4cc37b8651e309713c1f4d9a18e.tar.xz
MIPS: Loongson: Remove set_irq_trigger_mode()
set_irq_trigger_mode() is not needed on all platforms so remove it and move the related source code to mach_init_irq(). This will allow gdium to share the common irq.c without adding an empty set_irq_trigger_mode(). Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1493/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/loongson/fuloong-2e')
-rw-r--r--arch/mips/loongson/fuloong-2e/irq.c11
1 files changed, 4 insertions, 7 deletions
diff --git a/arch/mips/loongson/fuloong-2e/irq.c b/arch/mips/loongson/fuloong-2e/irq.c
index 320e9379bdd7..99e08c3db3f4 100644
--- a/arch/mips/loongson/fuloong-2e/irq.c
+++ b/arch/mips/loongson/fuloong-2e/irq.c
@@ -44,13 +44,6 @@ static struct irqaction cascade_irqaction = {
.name = "cascade",
};
-void __init set_irq_trigger_mode(void)
-{
- /* most bonito irq should be level triggered */
- LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
- LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
-}
-
void __init mach_init_irq(void)
{
/* init all controller
@@ -59,6 +52,10 @@ void __init mach_init_irq(void)
* 32-63 ------> bonito irq
*/
+ /* most bonito irq should be level triggered */
+ LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
+ LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
+
/* Sets the first-level interrupt dispatcher. */
mips_cpu_irq_init();
init_i8259_irqs();