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| author | Markos Chandras <markos.chandras@imgtec.com> | 2014-07-18 13:51:31 +0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-09-22 15:35:52 +0400 |
| commit | 80bc94d10466c710158d5f30c43625ed9fa59e78 (patch) | |
| tree | d91cca1d045d8fccf6503747459a027114c239b3 /arch/mips/include | |
| parent | fb02035083d9e2de1deba529b45835a698944f07 (diff) | |
| download | linux-80bc94d10466c710158d5f30c43625ed9fa59e78.tar.xz | |
MIPS: pgtable-bits: Define the CCA bit for WC writes on Ingenic cores
Ingenic uses the CCA:1 bit to achieve write-combine memory writes.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7401/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/asm/pgtable-bits.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index 011b0dcf306e..e747bfa0be7e 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -240,6 +240,11 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */ #define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */ +#elif defined(CONFIG_MACH_JZ4740) + +/* Ingenic uses the WA bit to achieve write-combine memory writes */ +#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT) + #endif #ifndef _CACHE_CACHABLE_NO_WA |