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authorTim Anderson <tanderson@mvista.com>2009-06-18 03:21:19 +0400
committerRalf Baechle <ralf@linux-mips.org>2009-07-03 18:45:25 +0400
commit9306c8def6abc2dbde4ac75eb6c631606b8fc1dd (patch)
tree4896cca4c6b27fa42e6f51d93c0a4f86b6f6fa3e /arch/mips/include
parentb53d4d1f8d522342e66f79b8b49a19835071fed4 (diff)
downloadlinux-9306c8def6abc2dbde4ac75eb6c631606b8fc1dd.tar.xz
MIPS: CMP: Extend the GIC IPI interrupts beyond 32
This patch extends the GIC interrupt handling beyond the current 32 bit range as well as extending the number of interrupts based on the number of CPUs. Signed-off-by: Tim Anderson <tanderson@mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/gic.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
index 954807d9d66a..e8fdd92c52c7 100644
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -20,7 +20,11 @@
#define GIC_TRIG_EDGE 1
#define GIC_TRIG_LEVEL 0
+#if CONFIG_SMP
+#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
+#else
#define GIC_NUM_INTRS 32
+#endif
#define MSK(n) ((1 << (n)) - 1)
#define REG32(addr) (*(volatile unsigned int *) (addr))