diff options
| author | Jayachandran C <jayachandranc@netlogicmicro.com> | 2012-07-24 19:28:47 +0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2012-07-24 19:28:47 +0400 |
| commit | 51d1eac0cd633b58be2a1e4e75765dc5bf913e6b (patch) | |
| tree | 07b89a6618a68337f43138c9742617b9b71dba40 /arch/mips/include | |
| parent | cedc8ef87c3349a6645e285f920715380dd25ddc (diff) | |
| download | linux-51d1eac0cd633b58be2a1e4e75765dc5bf913e6b.tar.xz | |
MIPS: Netlogic: SMP wakeup code update
Update for core intialization code. Initialize status register
after receiving NMI for CPU wakeup. Add the low level L1D flush
code before enabling threads in core.
Also convert the ehb to _ehb so that it works under more GCC
versions.
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3755/
Patchwork: https://patchwork.linux-mips.org/patch/4095/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h index bf7d41deb9be..7b63a6b722a0 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h @@ -47,7 +47,9 @@ #define CPU_BLOCKID_MAP 10 #define LSU_DEFEATURE 0x304 -#define LSU_CERRLOG_REGID 0x09 +#define LSU_DEBUG_ADDR 0x305 +#define LSU_DEBUG_DATA0 0x306 +#define LSU_CERRLOG_REGID 0x309 #define SCHED_DEFEATURE 0x700 /* Offsets of interest from the 'MAP' Block */ |