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authorJonas Gorski <jogo@openwrt.org>2013-06-18 12:34:32 +0400
committerRalf Baechle <ralf@linux-mips.org>2013-07-01 17:10:59 +0400
commit7ac836ce2aa7b931f6347e554cb65f9e9cc1da57 (patch)
tree13b99f09142adc6265dc5cf69b9574b411926471 /arch/mips/include
parenta068dde168e0c618e1dc2151a0922254ec3bbf04 (diff)
downloadlinux-7ac836ce2aa7b931f6347e554cb65f9e9cc1da57.tar.xz
MIPS: BCM63xx: Enable second core SMP on BCM6328 if available
BCM6328 has a OTP which tells us if the second core is available. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/5490/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h7
2 files changed, 9 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 9d3c08e4a7e4..22390a2a0661 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -296,6 +296,8 @@ enum bcm63xx_regs_set {
#define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
#define BCM_6328_RNG_BASE (0xdeadbeef)
#define BCM_6328_MISC_BASE (0xb0001800)
+#define BCM_6328_OTP_BASE (0xb0000600)
+
/*
* 6338 register sets base address
*/
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 654213746b32..018628fe6f15 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -1477,4 +1477,11 @@
#define PCIE_DEVICE_OFFSET 0x8000
+/*************************************************************************
+ * _REG relative to RSET_OTP
+ *************************************************************************/
+
+#define OTP_USER_BITS_6328_REG(i) (0x20 + (i) * 4)
+#define OTP_6328_REG3_TP1_DISABLED BIT(9)
+
#endif /* BCM63XX_REGS_H_ */