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author | Linus Torvalds <torvalds@linux-foundation.org> | 2018-12-26 21:45:33 +0300 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2018-12-26 21:45:33 +0300 |
commit | 89261c57021352045c4af24522c6854c9ee90139 (patch) | |
tree | ad7e2fd28eb7cc6700807b4c6cdc546959563bc8 /arch/mips/include/asm/pgtable.h | |
parent | c2f1f3e0e17d94ab0c66d83e669492cb9e9a3698 (diff) | |
parent | adcc81f148d733b7e8e641300c5590a2cdc13bf3 (diff) | |
download | linux-89261c57021352045c4af24522c6854c9ee90139.tar.xz |
Merge tag 'mips_4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Paul Burton:
"Here's the main MIPS pull for Linux 4.21. Core architecture changes
include:
- Syscall tables & definitions for unistd.h are now generated by
scripts, providing greater consistency with other architectures &
making it easier to add new syscalls.
- Support for building kernels with no floating point support, upon
which any userland attempting to use floating point instructions
will receive a SIGILL. Mostly useful to shrink the kernel & as
preparation for nanoMIPS support which does not yet include FP.
- MIPS SIMD Architecture (MSA) vector register context is now exposed
by ptrace via a new NT_MIPS_MSA regset.
- ASIDs are now stored as 64b values even for MIPS32 kernels,
expanding the ASID version field sufficiently that we don't need to
worry about overflow & avoiding rare issues with reused ASIDs that
have been observed in the wild.
- The branch delay slot "emulation" page is now mapped without write
permission for the user, preventing its use as a nice location for
attacks to execute malicious code from.
- Support for ioremap_prot(), primarily to allow gdb or other ptrace
users the ability to view their tracee's memory using the same
cache coherency attribute.
- Optimizations to more cpu_has_* macros, allowing more to be
compile-time constant where possible.
- Enable building the whole kernel with UBSAN instrumentation.
- Enable building the kernel with link-time dead code & data
elimination.
Platform specific changes include:
- The Boston board gains a workaround for DMA prefetching issues with
the EG20T Platform Controller Hub that it uses.
- Cleanups to Cavium Octeon code removing about 20k lines of
redundant code, mostly unused or duplicate register definitions in
headers.
- defconfig updates for the DECstation machines, including new
defconfigs for r4k & 64b machines.
- Further work on Loongson 3 support.
- DMA fixes for SiByte machines"
* tag 'mips_4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (95 commits)
MIPS: math-emu: Write-protect delay slot emulation pages
MIPS: Remove struct mm_context_t fp_mode_switching field
mips: generate uapi header and system call table files
mips: add system call table generation support
mips: remove syscall table entries
mips: add +1 to __NR_syscalls in uapi header
mips: rename scall64-64.S to scall64-n64.S
mips: remove unused macros
mips: add __NR_syscalls along with __NR_Linux_syscalls
MIPS: Expand MIPS32 ASIDs to 64 bits
MIPS: OCTEON: delete redundant register definitions
MIPS: OCTEON: cvmx_gmxx_inf_mode: use oldest forward compatible definition
MIPS: OCTEON: cvmx_mio_fus_dat3: use oldest forward compatible definition
MIPS: OCTEON: cvmx_pko_mem_debug8: use oldest forward compatible definition
MIPS: OCTEON: octeon-usb: use common gpio_bit definition
MIPS: OCTEON: enable all OCTEON drivers in defconfig
mips: annotate implicit fall throughs
MIPS: Hardcode cpu_has_mips* where target ISA allows
MIPS: MT: Remove norps command line parameter
MIPS: Only include mmzone.h when CONFIG_NEED_MULTIPLE_NODES=y
...
Diffstat (limited to 'arch/mips/include/asm/pgtable.h')
-rw-r--r-- | arch/mips/include/asm/pgtable.h | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index 129e0328367f..57933fc8fd98 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -214,8 +214,8 @@ static inline void set_pte(pte_t *ptep, pte_t pteval) if (kernel_uses_llsc && R10000_LLSC_WAR) { __asm__ __volatile__ ( - " .set arch=r4000 \n" " .set push \n" + " .set arch=r4000 \n" " .set noreorder \n" "1:" __LL "%[tmp], %[buddy] \n" " bnez %[tmp], 2f \n" @@ -225,13 +225,12 @@ static inline void set_pte(pte_t *ptep, pte_t pteval) " nop \n" "2: \n" " .set pop \n" - " .set mips0 \n" : [buddy] "+m" (buddy->pte), [tmp] "=&r" (tmp) : [global] "r" (page_global)); } else if (kernel_uses_llsc) { __asm__ __volatile__ ( - " .set "MIPS_ISA_ARCH_LEVEL" \n" " .set push \n" + " .set "MIPS_ISA_ARCH_LEVEL" \n" " .set noreorder \n" "1:" __LL "%[tmp], %[buddy] \n" " bnez %[tmp], 2f \n" @@ -241,7 +240,6 @@ static inline void set_pte(pte_t *ptep, pte_t pteval) " nop \n" "2: \n" " .set pop \n" - " .set mips0 \n" : [buddy] "+m" (buddy->pte), [tmp] "=&r" (tmp) : [global] "r" (page_global)); } |