diff options
| author | Jayachandran C <jchandra@broadcom.com> | 2013-12-21 15:22:13 +0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-01-25 01:39:46 +0400 |
| commit | c24a8a7a99885d5b986f38f6631f69e7794a3e5e (patch) | |
| tree | a0d6702fc1c45cba157a5734215c509fa4b216c6 /arch/mips/include/asm/netlogic/xlp-hal/pic.h | |
| parent | 27547abf36af7964b53a8c9265e266df692d4806 (diff) | |
| download | linux-c24a8a7a99885d5b986f38f6631f69e7794a3e5e.tar.xz | |
MIPS: Netlogic: Add MSI support for XLP
Add MSI chip and MSIX chip definitions.
For MSI, we map the link interrupt to a MSI link IRQ which will
do a second level of dispatch based on the MSI status register.
The MSI chip definitions use the MSI enable register to enable
and disable the MSI irqs.
For MSI-X, we split the 32 available MSI-X vectors across the
four PCIe links (8 each). These PIC interrupts generate an IRQ
per link which uses a second level dispatch as well.
The MSI-X chip definition uses the standard functions to enable
and disable interrupts.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6270/
Diffstat (limited to 'arch/mips/include/asm/netlogic/xlp-hal/pic.h')
| -rw-r--r-- | arch/mips/include/asm/netlogic/xlp-hal/pic.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h index 105389b79f09..3fcbe7409177 100644 --- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h +++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h @@ -193,14 +193,9 @@ #define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX) #define PIC_CLOCK_TIMER 7 -#define PIC_IRQ_BASE 8 #if !defined(LOCORE) && !defined(__ASSEMBLY__) -#define PIC_IRT_FIRST_IRQ (PIC_IRQ_BASE) -#define PIC_IRT_LAST_IRQ 63 -#define PIC_IRQ_IS_IRT(irq) ((irq) >= PIC_IRT_FIRST_IRQ) - /* * Misc */ |