diff options
| author | Markos Chandras <markos.chandras@imgtec.com> | 2014-11-10 15:25:34 +0300 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-11-24 09:44:05 +0300 |
| commit | cf0a8aa0226da5de88011e7f30eff22a894b2f49 (patch) | |
| tree | b508470022cd20f8cf0fcb8be10ee7f2904e07bc /arch/mips/include/asm/mipsregs.h | |
| parent | 4ec8f9e9b08451303253249e4e302f10ee23d565 (diff) | |
| download | linux-cf0a8aa0226da5de88011e7f30eff22a894b2f49.tar.xz | |
MIPS: cpu-probe: Set the FTLB probability bit on supported cores
Make use of the Config6/FLTBP bit to set the probability of a TLBWR
instruction to hit the FTLB or the VTLB. A value of 0 (which may be
the default value on certain cores, such as proAptiv or P5600)
means that a TLBWR instruction will never hit the VTLB which
leads to performance limitations since it effectively decreases
the number of available TLB slots.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: <stable@vger.kernel.org> # v3.15+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8368/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mipsregs.h')
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index b46cd220a018..22a135ac91de 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -661,6 +661,8 @@ #define MIPS_CONF6_SYND (_ULCAST_(1) << 13) /* proAptiv FTLB on/off bit */ #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15) +/* FTLB probability bits */ +#define MIPS_CONF6_FTLBP_SHIFT (16) #define MIPS_CONF7_WII (_ULCAST_(1) << 31) |