diff options
author | Wu Zhangjin <wuzhangjin@gmail.com> | 2009-11-16 20:32:59 +0300 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2009-12-17 04:57:20 +0300 |
commit | f8ede0f700f5478851f242f291d203cde54ca6cf (patch) | |
tree | 37fba17288bcd12468c454eb6c585d72fb6f9770 /arch/mips/include/asm/mach-loongson/loongson.h | |
parent | 9726b43a4d7aaa5b30f559e78768aeb3d17bc224 (diff) | |
download | linux-f8ede0f700f5478851f242f291d203cde54ca6cf.tar.xz |
MIPS: Loongson 2F: Add CPU frequency scaling support
Loongson 2F supports CPU clock scaling. When put it into wait mode by
setting the frequency as ZERO it will stay in this mode until an external
interrupt wakes the CPU again.
To enable clock scaling support, an external timer of a known stable rate
is required.
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: cpufreq@vger.kernel.org,
Cc: Dave Jones <davej@redhat.com>,
Cc: Dominik Brodowski <linux@dominikbrodowski.net>,
Cc: yanh@lemote.com
Cc: huhb@lemote.com,
Patchwork: http://patchwork.linux-mips.org/patch/660/
Patchwork: http://patchwork.linux-mips.org/patch/751/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-loongson/loongson.h')
-rw-r--r-- | arch/mips/include/asm/mach-loongson/loongson.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index 9bccdb5d4b51..a7fa66e85988 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -226,8 +226,12 @@ extern void mach_irq_dispatch(unsigned int pending); #define LOONGSON_PCIMAP_WIN(WIN, ADDR) \ ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) -/* Chip Config */ #ifdef CONFIG_CPU_SUPPORTS_CPUFREQ +#include <linux/cpufreq.h> +extern void loongson2_cpu_wait(void); +extern struct cpufreq_frequency_table loongson2_clockmod_table[]; + +/* Chip Config */ #define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80) #endif |