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authorJohn Crispin <blogic@openwrt.org>2012-05-20 02:33:56 +0400
committerJohn Crispin <blogic@openwrt.org>2012-09-13 12:30:58 +0400
commite316cb2b16bbfbe48387b56e7e6b5d32ec686f82 (patch)
tree8a57137909fa0a7911fe95aba9fb63130b2e3c66 /arch/mips/include/asm/mach-lantiq
parent3f8c50c9b110dad4136ea7226cd87b0c4cdb70c8 (diff)
downloadlinux-e316cb2b16bbfbe48387b56e7e6b5d32ec686f82.tar.xz
OF: pinctrl: MIPS: lantiq: adds support for FALCON SoC
Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks of up to 32 pins. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org
Diffstat (limited to 'arch/mips/include/asm/mach-lantiq')
-rw-r--r--arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
index b385252584ee..fccac3592651 100644
--- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
@@ -57,6 +57,10 @@ extern __iomem void *ltq_sys1_membase;
#define ltq_sys1_w32_mask(clear, set, reg) \
ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
+/* allow the gpio and pinctrl drivers to talk to eachother */
+extern int pinctrl_falcon_get_range_size(int id);
+extern void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range);
+
/*
* to keep the irq code generic we need to define this to 0 as falcon
* has no EIU/EBU