MIPS: Move headfiles to new location below arch/mips/include

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

4 files changed, 118 insertions, 0 deletions

diff --git a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
new file mode 100644
index 000000000000..9c8735158da1
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
@@ -0,0 +1,44 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 07 Ralf Baechle
+ */
+#ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * IP22 with a variety of processors so we can't use defaults for everything.
+ */
+#define cpu_has_tlb		1
+#define cpu_has_4kex		1
+#define cpu_has_4k_cache	1
+#define cpu_has_fpu		1
+#define cpu_has_32fpr		1
+#define cpu_has_counter		1
+#define cpu_has_mips16		0
+#define cpu_has_divec		0
+#define cpu_has_cache_cdex_p	1
+#define cpu_has_prefetch	0
+#define cpu_has_mcheck		0
+#define cpu_has_ejtag		0
+
+#define cpu_has_llsc		1
+#define cpu_has_vtag_icache	0		/* Needs to change for R8000 */
+#define cpu_has_dc_aliases	(PAGE_SIZE < 0x4000)
+#define cpu_has_ic_fills_f_dc	0
+
+#define cpu_has_dsp		0
+#define cpu_has_mipsmt		0
+#define cpu_has_userlocal	0
+
+#define cpu_has_nofpuex		0
+#define cpu_has_64bits		1
+
+#define cpu_has_mips32r1	0
+#define cpu_has_mips32r2	0
+#define cpu_has_mips64r1	0
+#define cpu_has_mips64r2	0
+
+#endif /* __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ip22/ds1286.h b/arch/mips/include/asm/mach-ip22/ds1286.h
new file mode 100644
index 000000000000..f19f1eafbc71
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip22/ds1286.h
@@ -0,0 +1,18 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2001, 03 by Ralf Baechle
+ *
+ * RTC routines for PC style attached Dallas chip.
+ */
+#ifndef __ASM_MACH_IP22_DS1286_H
+#define __ASM_MACH_IP22_DS1286_H
+
+#include <asm/sgi/hpc3.h>
+
+#define rtc_read(reg)		(hpc3c0->rtcregs[(reg)] & 0xff)
+#define rtc_write(data, reg)	do { hpc3c0->rtcregs[(reg)] = (data); } while(0)
+
+#endif /* __ASM_MACH_IP22_DS1286_H */
diff --git a/arch/mips/include/asm/mach-ip22/spaces.h b/arch/mips/include/asm/mach-ip22/spaces.h
new file mode 100644
index 000000000000..7f9fa6f66059
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip22/spaces.h
@@ -0,0 +1,27 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_MACH_IP22_SPACES_H
+#define _ASM_MACH_IP22_SPACES_H
+
+
+#ifdef CONFIG_64BIT
+
+#define PAGE_OFFSET		0xffffffff80000000UL
+
+#define CAC_BASE		0xffffffff80000000
+#define IO_BASE			0xffffffffa0000000
+#define UNCAC_BASE		0xffffffffa0000000
+#define MAP_BASE		0xc000000000000000
+
+#endif /* CONFIG_64BIT */
+
+#include <asm/mach-generic/spaces.h>
+
+#endif /* __ASM_MACH_IP22_SPACES_H */
diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
new file mode 100644
index 000000000000..a44fa9656a82
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -0,0 +1,29 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_IP22_WAR_H
+#define __ASM_MIPS_MACH_IP22_WAR_H
+
+/*
+ * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
+ */
+
+#define R4600_V1_INDEX_ICACHEOP_WAR	1
+#define R4600_V1_HIT_CACHEOP_WAR	1
+#define R4600_V2_HIT_CACHEOP_WAR	1
+#define R5432_CP0_INTERRUPT_WAR		0
+#define BCM1250_M3_WAR			0
+#define SIBYTE_1956_WAR			0
+#define MIPS4K_ICACHE_REFILL_WAR	0
+#define MIPS_CACHE_SYNC_WAR		0
+#define TX49XX_ICACHE_INDEX_INV_WAR	0
+#define RM9000_CDEX_SMP_WAR		0
+#define ICACHE_REFILLS_WORKAROUND_WAR	0
+#define R10000_LLSC_WAR			0
+#define MIPS34K_MISSED_ITLB_WAR		0
+
+#endif /* __ASM_MIPS_MACH_IP22_WAR_H */