diff options
| author | Chandrakala Chavva <cchavva@caviumnetworks.com> | 2015-01-15 16:11:17 +0300 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-02-20 17:32:46 +0300 |
| commit | ac6d9b3a03930820bec0ebd3a28f9dae32d27342 (patch) | |
| tree | 69bd6e7b723955f113e977f4f392da9c7de0f469 /arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h | |
| parent | 920cda3870557a50105f0c5eb783059b3aced86e (diff) | |
| download | linux-ac6d9b3a03930820bec0ebd3a28f9dae32d27342.tar.xz | |
MIPS: OCTEON: More OCTEONIII support
Read clock rate from the correct CSR. Don't clear COP0_DCACHE for OCTEONIII.
Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8945/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h')
| -rw-r--r-- | arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h index 4bef539e1f07..cf92fe733995 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h +++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h @@ -80,6 +80,9 @@ mfc0 v0, CP0_PRID_REG bbit0 v0, 15, 1f # OCTEON II or better have bit 15 set. Clear the error bits. + and t1, v0, 0xff00 + dli v0, 0x9500 + bge t1, v0, 1f # OCTEON III has no DCACHE_ERR_REG COP0 dli v0, 0x27 dmtc0 v0, CP0_DCACHE_ERR_REG 1: |