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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-11-04 00:28:14 +0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-11-04 00:28:14 +0400 |
| commit | d6748066ad0e8b2514545998f8367ebb3906f299 (patch) | |
| tree | f7a9bfd764a8fb781aeda0ef2249afbab42dddf7 /arch/mips/include/asm/mach-au1x00/au1xxx_psc.h | |
| parent | f04c045f8ce69c22bda9d99eb927276b776135fc (diff) | |
| parent | 3ba1e543ab4b02640d396098f2f6a199560d5f2d (diff) | |
| download | linux-d6748066ad0e8b2514545998f8367ebb3906f299.tar.xz | |
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (37 commits)
MIPS: O32: Provide definition of registers ta0 .. ta3.
MIPS: perf: Add Octeon support for hardware perf.
MIPS: perf: Add support for 64-bit perf counters.
MIPS: perf: Reorganize contents of perf support files.
MIPS: perf: Cleanup formatting in arch/mips/kernel/perf_event.c
MIPS: Add accessor macros for 64-bit performance counter registers.
MIPS: Add probes for more Octeon II CPUs.
MIPS: Add more CPU identifiers for Octeon II CPUs.
MIPS: XLR, XLS: Add comment for smp setup
MIPS: JZ4740: GPIO: Check correct IRQ in demux handler
MIPS: JZ4740: GPIO: Simplify IRQ demuxer
MIPS: JZ4740: Use generic irq chip
MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines
MIPS: Alchemy: kill au1xxx.h header
MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? defines
MIPS, IDE: Alchem, au1xxx-ide: Remove pb1200/db1200 header dep
MIPS: Alchemy: Redo PCI as platform driver
MIPS: Alchemy: more base address cleanup
MIPS: Alchemy: rewrite USB platform setup.
MIPS: Alchemy: abstract USB block control register access
...
Fix up trivial conflicts in:
arch/mips/alchemy/devboards/db1x00/platform.c
drivers/ide/Kconfig
drivers/mmc/host/au1xmmc.c
drivers/video/Kconfig
sound/mips/Kconfig
Diffstat (limited to 'arch/mips/include/asm/mach-au1x00/au1xxx_psc.h')
| -rw-r--r-- | arch/mips/include/asm/mach-au1x00/au1xxx_psc.h | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h index 5a5cb7386427..4e3f3bc26c60 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h @@ -33,19 +33,6 @@ #ifndef _AU1000_PSC_H_ #define _AU1000_PSC_H_ -/* The PSC base addresses. */ -#ifdef CONFIG_SOC_AU1550 -#define PSC0_BASE_ADDR 0xb1a00000 -#define PSC1_BASE_ADDR 0xb1b00000 -#define PSC2_BASE_ADDR 0xb0a00000 -#define PSC3_BASE_ADDR 0xb0b00000 -#endif - -#ifdef CONFIG_SOC_AU1200 -#define PSC0_BASE_ADDR 0xb1a00000 -#define PSC1_BASE_ADDR 0xb1b00000 -#endif - /* * The PSC select and control registers are common to all protocols. */ @@ -80,19 +67,6 @@ #define PSC_AC97GPO_OFFSET 0x00000028 #define PSC_AC97GPI_OFFSET 0x0000002c -#define AC97_PSC_SEL (AC97_PSC_BASE + PSC_SEL_OFFSET) -#define AC97_PSC_CTRL (AC97_PSC_BASE + PSC_CTRL_OFFSET) -#define PSC_AC97CFG (AC97_PSC_BASE + PSC_AC97CFG_OFFSET) -#define PSC_AC97MSK (AC97_PSC_BASE + PSC_AC97MSK_OFFSET) -#define PSC_AC97PCR (AC97_PSC_BASE + PSC_AC97PCR_OFFSET) -#define PSC_AC97STAT (AC97_PSC_BASE + PSC_AC97STAT_OFFSET) -#define PSC_AC97EVNT (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET) -#define PSC_AC97TXRX (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET) -#define PSC_AC97CDC (AC97_PSC_BASE + PSC_AC97CDC_OFFSET) -#define PSC_AC97RST (AC97_PSC_BASE + PSC_AC97RST_OFFSET) -#define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET) -#define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET) - /* AC97 Config Register. */ #define PSC_AC97CFG_RT_MASK (3 << 30) #define PSC_AC97CFG_RT_FIFO1 (0 << 30) |