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| author | Ralf Baechle <ralf@linux-mips.org> | 2014-12-17 13:46:40 +0300 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-01-13 17:53:08 +0300 |
| commit | d33e6fe3ca74108e8e6ea1f5560b21c834b579a5 (patch) | |
| tree | a0cfa87a74d3d715df35cc6d02423bca00e474e7 /arch/mips/include/asm/fpu.h | |
| parent | b0c34f6155e2d8bbe096a85a770d63ee6be6c726 (diff) | |
| download | linux-d33e6fe3ca74108e8e6ea1f5560b21c834b579a5.tar.xz | |
MIPS: FRE: Use set/clear_c0_config5 instead of open coded sequences.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/fpu.h')
| -rw-r--r-- | arch/mips/include/asm/fpu.h | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h index 5528f4e2af6a..affebb78f5d6 100644 --- a/arch/mips/include/asm/fpu.h +++ b/arch/mips/include/asm/fpu.h @@ -64,7 +64,7 @@ static inline int __enable_fpu(enum fpu_mode mode) return SIGFPE; /* set FRE */ - write_c0_config5(read_c0_config5() | MIPS_CONF5_FRE); + set_c0_config5(MIPS_CONF5_FRE); goto fr_common; case FPU_64BIT: @@ -76,7 +76,7 @@ static inline int __enable_fpu(enum fpu_mode mode) case FPU_32BIT: if (cpu_has_fre) { /* clear FRE */ - write_c0_config5(read_c0_config5() & ~MIPS_CONF5_FRE); + clear_c0_config5(MIPS_CONF5_FRE); } fr_common: /* set CU1 & change FR appropriately */ @@ -196,15 +196,13 @@ static inline int init_fpu(void) return 0; } - config5 = read_c0_config5(); - /* * Ensure FRE is clear whilst running _init_fpu, since * single precision FP instructions are used. If FRE * was set then we'll just end up initialising all 32 * 64b registers. */ - write_c0_config5(config5 & ~MIPS_CONF5_FRE); + config5 = clear_c0_config5(MIPS_CONF5_FRE); enable_fpu_hazard(); _init_fpu(); |