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author | Ingo Molnar <mingo@elte.hu> | 2010-02-08 10:55:43 +0300 |
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committer | Ingo Molnar <mingo@elte.hu> | 2010-02-08 10:55:46 +0300 |
commit | 6d3e0907b8b239d16720d144e2675ecf10d3bc3b (patch) | |
tree | e0b0743b5f6f82b057cafc4f3687396a6e01a0b4 /arch/mips/include/asm/cpu-info.h | |
parent | 23577256953c870de9b724c3a2611ce7be6a1e4e (diff) | |
parent | 50200df462023b187d80a99a52f5f2cfe3c86c26 (diff) | |
download | linux-6d3e0907b8b239d16720d144e2675ecf10d3bc3b.tar.xz |
Merge branch 'sched/urgent' into sched/core
Merge reason: Merge dependent fix, update to latest -rc.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/mips/include/asm/cpu-info.h')
-rw-r--r-- | arch/mips/include/asm/cpu-info.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h index 126044308dec..b39def3f6e03 100644 --- a/arch/mips/include/asm/cpu-info.h +++ b/arch/mips/include/asm/cpu-info.h @@ -58,6 +58,9 @@ struct cpuinfo_mips { struct cache_desc tcache; /* Tertiary/split secondary cache */ int srsets; /* Shadow register sets */ int core; /* physical core number */ +#ifdef CONFIG_64BIT + int vmbits; /* Virtual memory size in bits */ +#endif #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) /* * In the MIPS MT "SMTC" model, each TC is considered |