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| author | Ralf Baechle <ralf@linux-mips.org> | 2013-06-26 19:06:34 +0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2013-07-01 17:10:56 +0400 |
| commit | 1990e5429c2149a30a81ff634215c1aa76560a89 (patch) | |
| tree | 5362bc3d4fb96b32c43d01104968428487e7e685 /arch/mips/include/asm/cpu-features.h | |
| parent | 0dad5d262278d24babbd62241fd238a3a3a0a39a (diff) | |
| download | linux-1990e5429c2149a30a81ff634215c1aa76560a89.tar.xz | |
MIPS: Get rid of MIPS I flag and test macros.
MIPS I is the ancestor of all MIPS ISA and architecture variants. Anything
ever build in the MIPS empire is either MIPS I or at least contains MIPS I.
If it's running Linux, that is.
So there is little point in having cpu_has_mips_1 because it will always
evaluate as true - though usually only at runtime. Thus there is no
point in having the MIPS_CPU_ISA_I ISA flag, so get rid of it.
Little complication: traps.c was using a test for a pure MIPS I ISA as
a test for an R3000-style cp0. To deal with that, use a check for
cpu_has_3kex or cpu_has_4kex instead.
cpu_has_3kex is a new macro. At the moment its default implementation is
!cpu_has_4kex but this may eventually change if Linux is ever going to
support the oddball MIPS processors R6000 and R8000 so users of either
of these macros should not make any assumptions.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/5551/
Diffstat (limited to 'arch/mips/include/asm/cpu-features.h')
| -rw-r--r-- | arch/mips/include/asm/cpu-features.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index e5ec8fcd8afa..9609812bc8f2 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -24,6 +24,16 @@ #ifndef cpu_has_tlb #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) #endif + +/* + * For the moment we don't consider R6000 and R8000 so we can assume that + * anything that doesn't support R4000-style exceptions and interrupts is + * R3000-like. Users should still treat these two macro definitions as + * opaque. + */ +#ifndef cpu_has_3kex +#define cpu_has_3kex (!cpu_has_4kex) +#endif #ifndef cpu_has_4kex #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) #endif @@ -136,7 +146,6 @@ #endif #endif -# define cpu_has_mips_1 (cpu_data[0].isa_level & MIPS_CPU_ISA_I) #ifndef cpu_has_mips_2 # define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II) #endif |