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| author | Paul Burton <paul.burton@mips.com> | 2019-10-02 00:53:10 +0300 |
|---|---|---|
| committer | Paul Burton <paul.burton@mips.com> | 2019-10-07 19:42:20 +0300 |
| commit | 05e6da742b5b708057e84487576655e4d7238dd1 (patch) | |
| tree | 8b65fb2ecd7934b41e505afa731916913243b470 /arch/mips/include/asm/barrier.h | |
| parent | 21e3134b3ec09e722cbcda69788f206adc8db1f4 (diff) | |
| download | linux-05e6da742b5b708057e84487576655e4d7238dd1.tar.xz | |
MIPS: barrier: Clean up __smp_mb() definition
We #ifdef on Cavium Octeon CPUs, but emit the same sync instruction in
both cases. Remove the #ifdef & simply expand to the __sync() macro.
Whilst here indent the strong ordering case definitions to match the
indentation of the weak ordering ones, helping readability.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: linux-kernel@vger.kernel.org
Diffstat (limited to 'arch/mips/include/asm/barrier.h')
| -rw-r--r-- | arch/mips/include/asm/barrier.h | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h index f36cab87cfde..8a5abc1c85a6 100644 --- a/arch/mips/include/asm/barrier.h +++ b/arch/mips/include/asm/barrier.h @@ -89,17 +89,13 @@ static inline void wmb(void) #endif /* !CONFIG_CPU_HAS_WB */ #if defined(CONFIG_WEAK_ORDERING) -# ifdef CONFIG_CPU_CAVIUM_OCTEON -# define __smp_mb() __sync() -# else -# define __smp_mb() __asm__ __volatile__("sync" : : :"memory") -# endif +# define __smp_mb() __sync() # define __smp_rmb() rmb() # define __smp_wmb() wmb() #else -#define __smp_mb() barrier() -#define __smp_rmb() barrier() -#define __smp_wmb() barrier() +# define __smp_mb() barrier() +# define __smp_rmb() barrier() +# define __smp_wmb() barrier() #endif /* |