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| author | Lars Povlsen <lars.povlsen@microchip.com> | 2020-05-13 16:23:47 +0300 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-05-14 01:27:19 +0300 |
| commit | d203c2d3eed5a6f1d617591335ccef7b1926461b (patch) | |
| tree | 6c736b1d410a090ff0dcc2f8ce1ddc1f08101da6 /arch/mips/boot | |
| parent | 125be5868eaa5ceb9d0b5a21e281aca6c9c16a9b (diff) | |
| download | linux-d203c2d3eed5a6f1d617591335ccef7b1926461b.tar.xz | |
MIPS: dts: mscc: Updated changed name for miim pinctrl function
This is an add-on patch to the main SoC Sparx5 series
(Message-ID: <20200513125532.24585-1-lars.povlsen@microchip.com>).
This changes the miim pinctrl function name from "miim1" to "miim" due
to refactoring in the driver, obsoleting the instance number.
The change in the driver was to better fit new platforms, as the
instance number is redundant information. Specifically, support for
the Microchip Sparx5 SoC is being submitted, where this change became
necessary.
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/boot')
| -rw-r--r-- | arch/mips/boot/dts/mscc/ocelot.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi index 797d336db54d..f94e8a02ed06 100644 --- a/arch/mips/boot/dts/mscc/ocelot.dtsi +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi @@ -214,7 +214,7 @@ miim1: miim1 { pins = "GPIO_14", "GPIO_15"; - function = "miim1"; + function = "miim"; }; }; |