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| author | Michal Simek <monstr@monstr.eu> | 2011-04-04 17:46:03 +0400 |
|---|---|---|
| committer | Michal Simek <monstr@monstr.eu> | 2012-03-23 12:28:18 +0400 |
| commit | 1451d1d88b9aa32ac9ee54180239e9b34b6f9e86 (patch) | |
| tree | 417fbc899c6469af1c0b2cf2dc1a99f050cf48fd /arch/microblaze | |
| parent | 95b0f9ea66661681f6ae081ea28416744d622c07 (diff) | |
| download | linux-1451d1d88b9aa32ac9ee54180239e9b34b6f9e86.tar.xz | |
microblaze: Introduce TLB skip size
TLB skip size direct how many TLBs is skipped.
Currently TLB0 and TLB1 are used for Linux kernel mapping
that's why their are skipped.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Diffstat (limited to 'arch/microblaze')
| -rw-r--r-- | arch/microblaze/include/asm/mmu.h | 1 | ||||
| -rw-r--r-- | arch/microblaze/kernel/hw_exception_handler.S | 7 | ||||
| -rw-r--r-- | arch/microblaze/kernel/misc.S | 4 |
3 files changed, 7 insertions, 5 deletions
diff --git a/arch/microblaze/include/asm/mmu.h b/arch/microblaze/include/asm/mmu.h index 8d6a654ceffb..5198de8b1224 100644 --- a/arch/microblaze/include/asm/mmu.h +++ b/arch/microblaze/include/asm/mmu.h @@ -68,6 +68,7 @@ extern void _tlbia(void); /* invalidate all TLB entries */ */ # define MICROBLAZE_TLB_SIZE 64 +# define MICROBLAZE_TLB_SKIP 2 /* * TLB entries are defined by a "high" tag portion and a "low" data diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S index e62be8379604..b7249f4215a2 100644 --- a/arch/microblaze/kernel/hw_exception_handler.S +++ b/arch/microblaze/kernel/hw_exception_handler.S @@ -821,18 +821,19 @@ ex_handler_done: * A common place to load the TLB. */ tlb_index: - .long 1 /* MS: storing last used tlb index */ + /* MS: storing last used tlb index */ + .long (MICROBLAZE_TLB_SKIP - 1) finish_tlb_load: /* MS: load the last used TLB index. */ lwi r5, r0, TOPHYS(tlb_index) addik r5, r5, 1 /* MS: inc tlb_index -> use next one */ /* MS: FIXME this is potential fault, because this is mask not count */ - andi r5, r5, (MICROBLAZE_TLB_SIZE-1) + andi r5, r5, MICROBLAZE_TLB_SIZE - 1 ori r6, r0, 1 cmp r31, r5, r6 blti r31, ex12 - addik r5, r6, 1 + addik r5, r6, MICROBLAZE_TLB_SKIP - 1 ex12: /* MS: save back current TLB index */ swi r5, r0, TOPHYS(tlb_index) diff --git a/arch/microblaze/kernel/misc.S b/arch/microblaze/kernel/misc.S index 206da3da361f..c9090d7973f6 100644 --- a/arch/microblaze/kernel/misc.S +++ b/arch/microblaze/kernel/misc.S @@ -36,7 +36,7 @@ _tlbia_1: nop mts rtlbhi, r0 /* flush: ensure V is clear */ nop - addik r11, r12, -2 + addik r11, r12, -MICROBLAZE_TLB_SKIP bneid r11, _tlbia_1 /* loop for all entries */ addik r12, r12, -1 /* sync */ @@ -75,7 +75,7 @@ early_console_reg_tlb_alloc: * Load a TLB entry for the UART, so that microblaze_progress() can use * the UARTs nice and early. We use a 4k real==virtual mapping. */ - ori r4, r0, MICROBLAZE_TLB_SIZE - 1 + ori r4, r0, 63 mts rtlbx, r4 /* TLB slot 63 */ or r4,r5,r0 |