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| author | David S. Miller <davem@davemloft.net> | 2012-10-09 21:14:32 +0400 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2012-10-09 21:14:32 +0400 |
| commit | 8dd9117cc7a021ced1c5cf177e2d44dd92b88617 (patch) | |
| tree | cad990f58f9ec6d400226dda86718fc10781416e /arch/m68k/platform/coldfire/m527x.c | |
| parent | 16e310ae6ed352c4963b1f2413fcd88fa693eeda (diff) | |
| parent | 547b1e81afe3119f7daf702cc03b158495535a25 (diff) | |
| download | linux-8dd9117cc7a021ced1c5cf177e2d44dd92b88617.tar.xz | |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux
Pulled mainline in order to get the UAPI infrastructure already
merged before I pull in David Howells's UAPI trees for networking.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/m68k/platform/coldfire/m527x.c')
| -rw-r--r-- | arch/m68k/platform/coldfire/m527x.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/m68k/platform/coldfire/m527x.c b/arch/m68k/platform/coldfire/m527x.c index b3cb378c5e94..1431ba03c602 100644 --- a/arch/m68k/platform/coldfire/m527x.c +++ b/arch/m68k/platform/coldfire/m527x.c @@ -53,9 +53,9 @@ static void __init m527x_uarts_init(void) /* * External Pin Mask Setting & Enable External Pin for Interface */ - sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART); + sepmask = readw(MCFGPIO_PAR_UART); sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK; - writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART); + writew(sepmask, MCFGPIO_PAR_UART); } /***************************************************************************/ @@ -67,19 +67,19 @@ static void __init m527x_fec_init(void) /* Set multi-function pins to ethernet mode for fec0 */ #if defined(CONFIG_M5271) - v = readb(MCF_IPSBAR + 0x100047); - writeb(v | 0xf0, MCF_IPSBAR + 0x100047); + v = readb(MCFGPIO_PAR_FECI2C); + writeb(v | 0xf0, MCFGPIO_PAR_FECI2C); #else - par = readw(MCF_IPSBAR + 0x100082); - writew(par | 0xf00, MCF_IPSBAR + 0x100082); - v = readb(MCF_IPSBAR + 0x100078); - writeb(v | 0xc0, MCF_IPSBAR + 0x100078); + par = readw(MCFGPIO_PAR_FECI2C); + writew(par | 0xf00, MCFGPIO_PAR_FECI2C); + v = readb(MCFGPIO_PAR_FEC0HL); + writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL); /* Set multi-function pins to ethernet mode for fec1 */ - par = readw(MCF_IPSBAR + 0x100082); - writew(par | 0xa0, MCF_IPSBAR + 0x100082); - v = readb(MCF_IPSBAR + 0x100079); - writeb(v | 0xc0, MCF_IPSBAR + 0x100079); + par = readw(MCFGPIO_PAR_FECI2C); + writew(par | 0xa0, MCFGPIO_PAR_FECI2C); + v = readb(MCFGPIO_PAR_FEC1HL); + writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL); #endif } |