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| author | Greg Ungerer <gerg@uclinux.org> | 2009-05-19 08:38:08 +0400 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2009-09-16 03:43:50 +0400 |
| commit | f2154bef817ac3d0ea67b52526fd8e88898b66f9 (patch) | |
| tree | 3ffa5cf5c3ec82a59f75728a580bd9332a32ebee /arch/m68k/include/asm/m5307sim.h | |
| parent | 5187995f0a9253e915dfee83684eae7b692213e6 (diff) | |
| download | linux-f2154bef817ac3d0ea67b52526fd8e88898b66f9.tar.xz | |
m68knommu: merge old ColdFire interrupt controller masking macros
Currently the code that supports setting the old style ColdFire interrupt
controller mask registers is macros in the include files of each of the
CPU types. Merge all these into a set of real masking functions in the
old Coldfire interrupt controller code proper. All the macros are basically
the same (excepting a register size difference on really early parts).
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m5307sim.h')
| -rw-r--r-- | arch/m68k/include/asm/m5307sim.h | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h index 6a1870c925a6..60946225699d 100644 --- a/arch/m68k/include/asm/m5307sim.h +++ b/arch/m68k/include/asm/m5307sim.h @@ -124,23 +124,6 @@ #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ -#if defined(CONFIG_M5307) -#define MCFSIM_IMR_MASKALL 0x3fffe /* All SIM intr sources */ -#endif - -/* - * Macro to set IMR register. It is 32 bits on the 5307. - */ -#define mcf_getimr() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) - -#define mcf_setimr(imr) \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); - -#define mcf_getipr() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR)) - - /* * Some symbol defines for the Parallel Port Pin Assignment Register */ |