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| author | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2009-03-27 18:14:38 +0300 |
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| committer | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2009-03-27 18:14:38 +0300 |
| commit | b92efa9abffc4a634cd2e7a0f81f8aa6310d67c9 (patch) | |
| tree | 9847508d9b8d4e585f90db4a453bfbc3700c997e /arch/m68k/include/asm/m523xsim.h | |
| parent | a16fffdd8eb95ebab7dc22414896fe6493951e0e (diff) | |
| parent | be0ea69674ed95e1e98cb3687a241badc756d228 (diff) | |
| download | linux-b92efa9abffc4a634cd2e7a0f81f8aa6310d67c9.tar.xz | |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 into avr32-arch
Diffstat (limited to 'arch/m68k/include/asm/m523xsim.h')
| -rw-r--r-- | arch/m68k/include/asm/m523xsim.h | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h new file mode 100644 index 000000000000..bf397313e93f --- /dev/null +++ b/arch/m68k/include/asm/m523xsim.h @@ -0,0 +1,45 @@ +/****************************************************************************/ + +/* + * m523xsim.h -- ColdFire 523x System Integration Module support. + * + * (C) Copyright 2003-2005, Greg Ungerer <gerg@snapgear.com> + */ + +/****************************************************************************/ +#ifndef m523xsim_h +#define m523xsim_h +/****************************************************************************/ + + +/* + * Define the 523x SIM register set addresses. + */ +#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ +#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ +#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ +#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ +#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ +#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ +#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ +#define MCFINTC_IRLR 0x18 /* */ +#define MCFINTC_IACKL 0x19 /* */ +#define MCFINTC_ICR0 0x40 /* Base ICR register */ + +#define MCFINT_VECBASE 64 /* Vector base number */ +#define MCFINT_UART0 13 /* Interrupt number for UART0 */ +#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ +#define MCFINT_QSPI 18 /* Interrupt number for QSPI */ + +/* + * SDRAM configuration registers. + */ +#define MCFSIM_DCR 0x44 /* SDRAM control */ +#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ +#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ +#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ +#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ + +/****************************************************************************/ +#endif /* m523xsim_h */ |