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authorMark Brown <broonie@opensource.wolfsonmicro.com>2011-04-18 20:12:14 +0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2011-04-18 20:12:14 +0400
commitfac56c2df51bc29b07b3c2dcfabf32a015a0522c (patch)
tree1ff5d84ecf4ea0bcbd42e2ef9624b5ade3810890 /arch/ia64/sn/pci
parent6caa15d0b84d2ea688fd31f4f172c8353463e109 (diff)
parenta6360dd37e1a144ed11e6548371bade559a1e4df (diff)
downloadlinux-fac56c2df51bc29b07b3c2dcfabf32a015a0522c.tar.xz
Merge commit 'v2.6.39-rc3' into for-2.6.39
Diffstat (limited to 'arch/ia64/sn/pci')
-rw-r--r--arch/ia64/sn/pci/pcibr/pcibr_dma.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_dma.c b/arch/ia64/sn/pci/pcibr/pcibr_dma.c
index c659ad5613a0..33def666a664 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_dma.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_dma.c
@@ -227,7 +227,7 @@ pcibr_dma_unmap(struct pci_dev *hwdev, dma_addr_t dma_handle, int direction)
* after doing the read. For PIC this routine then forces a fake interrupt
* on another line, which is logically associated with the slot that the PIO
* is addressed to. It then spins while watching the memory location that
- * the interrupt is targetted to. When the interrupt response arrives, we
+ * the interrupt is targeted to. When the interrupt response arrives, we
* are sure that the DMA has landed in memory and it is safe for the driver
* to proceed. For TIOCP use the Device(x) Write Request Buffer Flush
* Bridge register since it ensures the data has entered the coherence domain,