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| author | Guo Ren <ren_guo@c-sky.com> | 2018-09-05 09:25:10 +0300 |
|---|---|---|
| committer | Guo Ren <ren_guo@c-sky.com> | 2018-10-25 18:36:19 +0300 |
| commit | 00a9730e1007c6cc87a7c78af2f24a4105d616ee (patch) | |
| tree | c014e5a0606a7a88b6e3493f49862c040f9aeea8 /arch/csky/include/asm/cacheflush.h | |
| parent | 4859bfca11c7d63d55175bcd85a75d6cee4b7184 (diff) | |
| download | linux-00a9730e1007c6cc87a7c78af2f24a4105d616ee.tar.xz | |
csky: Cache and TLB routines
This patch adds cache and tlb sync codes for abiv1 & abiv2.
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/csky/include/asm/cacheflush.h')
| -rw-r--r-- | arch/csky/include/asm/cacheflush.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/csky/include/asm/cacheflush.h b/arch/csky/include/asm/cacheflush.h new file mode 100644 index 000000000000..a96da67261ae --- /dev/null +++ b/arch/csky/include/asm/cacheflush.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. + +#ifndef __ASM_CSKY_CACHEFLUSH_H +#define __ASM_CSKY_CACHEFLUSH_H + +#include <abi/cacheflush.h> + +#endif /* __ASM_CSKY_CACHEFLUSH_H */ |